U.S. Philips Corporation

Theodoor A Claasen

Wolfgang F Mecklenbrauker

Petrus J Van Gerwen

Johannes Bernhard Peek

Johannes W Bergmans

Johannes M Meijer

Nicolaas Van Hurck

Martinus L Didden

Gerardus F Beenker

Wilfred A Snijders

Arthur H Van Roermund

Hendrik Arie Van Essen

Johan M Schmidt

Gerardus C Gielis

Hendrik J Kotmans

Hans-Jurgen Butterweck

Albert J Stienstra

Petrus C Sommen

Harry B Schoonheijm

The transmitter (DTR) and the receiver (DRC) of a system for transmitting data signals at a given symbol rate 1/T comprise discrete-time smearing filters (SM and DSM) for combatting the effect of additive pulse-like disturbances (p'(t)) in the transmission channel (TCH). In many cases these disturbances (p'(t)) turn out to have a pronounced bandwidth-limited nature. By utilizing this feature the implementation of the smearing filters (SM and DSM) is simplfied and/or their performance level is improved in that the non-zero values of their impulse responses s(i) and d(j) only occur at the points of grids of the indices i and j recurring with a period of L, where L is an integer greater than 1 and where L is determined substantially by the ratio L.sub.0 of the symbol rate 1/T to twice the highest significant frequency f.sub.m of these disturbances (p'(t)).

Data transmission system comprising smearing filters

An arrangement for full-duplex data transmission over a two-wire circuit (1) comprises a transmit channel (2) connected to a baseband data transmitter (6) and including a smearing filter (18), a receive channel (3) connected to a baseband data receiver (9) and including a complementary smearing filter (19), a hybrid junction (4), an echo canceller (14) with an adaptive filter (15) and an adjusting circuit (16), and a combining circuit (17) inserted in the receive channel (3). Despite the application of the smearing filters (18, 19) the complexity of the echo canceller (14) is not increased as the arrangement comprises first and second delay means (20, 21) with a delay (D) corresponding to the signal delay of the cascade connection of the smearing filters (18, 19), the first delay means (20) having been inserted in a first signal path from the output of data transmitter (6) to the adjusting circuit (16) and the second delay means (21) having been inserted in a second signal path from the output of data transmitter (6) via the adaptive filter (15) and the combining circuit (17) to a point (P) in the receive channel (3) where the residual signal to be applied to the adjusting circuit (16) is tapped, and the complementary smearing filter (19) in the receive channel (3) has been inserted between the hybrid junction (4) and the tapping point (P) for the residual signal.

Arrangement for full-duplex data transmission over two-wire circuits

A frequency-domain block-adaptive digital filter (FDAF) having a finite impulse response of length N for filtering a time-domain input signal in accordance with the overlap-save method includes window means (11) for obtaining modifications (B(p;m)) of the 2N frequency-domain weighting factors (W(p;m)) from correlation products (A(p;m)). A known FDAF of this type contains five 2N-point FFT's, two of which are used in the window means (11). By utilizing a special time-domain window function which can be implemented very efficiently in the window means (11) with the aid of a frequency-domain convolution, a FDAF of this type containing only three 2N-point FFT's is obtained whose convergence properties are comparable to those of the known FDAF containing five 2N-point FFT's.

Frequency-domain block-adaptive digital filter

A data transmission system comprising a transversal smearing filter at the transmitting end and a transversal desmearing filter at the receiving end. To simplify the filters, at least the sequence of coefficients of the desmearing filter is formed by elements of the set {-1, 0, +1}, which results in an optimum smearing of noise pulses in the system compared with a system without such a filter.

Data transmission system

A transmission system for transmitting data signals in a modulation band comprising a transversal smearing filter at the transmitter end and a transversal desmearing filter at the receiver end. In order to obtain an optimum smearing efficiency, the sequence of real individual coefficients of the multiplying factors of the transversal desmearing filter satisfy the requirement that for a given upper limit for the intersymbol interference produced by the cascade arrangement formed by the smearing filter, and the desmearing filter a substantially maximum value is derived for a merit factor indicating by what factor the maximum value of a disturbance is decreased by including a smearing filter and a desmearing filter in the transmission system.

Transmission system for the transmission of data signals in a modulation

Multiplier circuit for multiplying an information signal x(t) by a periodic signal y(t) having frequency f.sub.o, more specifically for amplitude modulation purposes in a stereo decoder. The multiplier circuit comprises N switching circuits 21(k) wherein k=0, 1, . . . N-1 which are each connected to a clock pulse generator 221, 222 by means of a control channel 25(k) and are each connected to an input of an adder device 28 by means of a signal channel 26(k). In addition, each switching circuit 21(k) receives the information signal x(t). A series of clock pulses g(k;t) is applied to each control channel in such a manner that for the control channel having number k these clock pulses occur at the instants t.sub.o +k(T.sub.o /N)+iT.sub.o wherein t.sub.o represents a constant T.sub.o =1/f.sub.o and i=. . . , -2, -1, 0, 1, 2, . . . Each signal channel 26(k) comprises a weighting network 27(k) having a constant weighting factor W(k) defined by the relation W(k)=y(t.sub.o +k(T.sub.o /N)). Each control channel 25(k) (or each signal channel 26(k)) incorporates a pulse reshaping circuit 24(k), which converts a pulse applied thereto into a pulse having a width equal to .tau.=T.sub.o /M wherein M represents an integer, for example M=N-1.

Multiplier circuit for multiplying an information signal by a periodic

Method of a N-point discrete Fourier transform. The original set, consisting of N input signal values {a(k)}k=0,1,2, . . . N-1 is converted into two sets of signal values {b.sub.1 (q)}q=1,2, . . . M and {b.sub.2 (q)}q=1,2, . . . M, which each comprise M=(N-1)/2 signal values, each value being a linear combination of two of the original input signal values a(k). These sequences are circularly convolved with the impulse response h.sub.1 (v)=.alpha.cos((2.pi./N) g.sup.V) and h.sub.2 (v)=j.beta.sin ((2.pi./N) g.sup.V), respectively, for generating a set of third data elements y.sub.1 (p) and a set of fourth signal values y.sub.2 (p). Herein N is a prime and .alpha.,.beta. and g represent constants and it holds that p, v=1,2, . . . M, whereas j=.sqroot. -1. The desired output signal value can be obtained by means of a linear combination of the signal values y.sub.1 (p), y.sub.2 (p) and a(0).

Method of and arrangement for calculating the discrete Fourier transform

An FM-receiver with transmitter characterization, having a tuning unit, an IF-amplifier, a demodulation circuit for demodulating a discrete transmitter characterization signal, a clock regeneration circuit, a decoding device for decoding the discrete transmitter characterization signal and a signal processing unit. The clock regeneration circuit regenerates a clock signal the period of which is obtained by dividing the frequency of the stereo pilot signal. Synchronization of the clock signal phase with the phase of the clock signal used in the transmitter is carried out by detecting, using of a periodic window signal, the average phase of the code edges in the discrete transmitter characterization signal and by choosing the phase of the regenerated clock signal to be equal thereto.

FM-Receiver with transmitter characterization

An analog-to-digital converter is described for converting an analog-signal into a sequence of (b+a)-bit code words by means of a b-bit auxiliary analog-to-digital converter. To reduce the quantizing noise resulting from the requisite quantizing of the analog signal samples this analog signal is applied to an integrating network whose output is connected to an amplitude-limiting device which brings the integrated signal within the signal range of the auxiliary analog-to-digital converter, which in its turn produces a sequence of b-bit code words which are applied to a digital output filter via a cascade arrangement of an amplitude-restoration device and a difference network. Sampling pulses which occur at a frequency exceeding the Nyquist sampling frequency associated with the analog signal are applied to the auxiliary analog-to-digital converter.

(b+a)-Bit-A/D convertor with b-bit auxiliary A/D convertor

A digital-to-analog converter is described for converting (b+a)-bit code words into an analog signal by means of a b-bit auxiliary digital-to-analog converter. In order to reduce the quantizing noise introduced by the indispensible quantizing of the (b+a)-bit code words for obtaining the b-bit code words these (a+b)-bit code words are applied to an integrating network which has its output connected to an amplitude-limiting device which brings the integrated signal in the signal range of the auxiliary-D/A converter. The output signal of the amplitude-limiting device is now quantized and this quantizing signal is applied to the auxiliary D/A converter which produces analog output signal samples which are applied to, possibly, an analog output filter through a cascade arrangement of an amplitude-restorer and a difference network. The (b+a)-bit code words are assumed to occur with a frequency which is higher than the Nyquist sampling frequency associated with the analog signal represented by these (b+a)-bit code words.

(b+a)-Bit D/A converter with b-bit auxiliary D/A converter

A multiplex system has an inverse Fourier transformer that is unequal to its forward one, therefore an optimum distribution of elements is possible.

Arrangement for converting discrete signals into a discrete

Cross-correlation arrangement for determining the presence or absence of a signal x.sub.2 (t) of known frequency in an unknown signal x.sub.1 (t) if this signal x.sub.2 (t) is present for at least a period of time .tau..sub.o with an unknown starting instant. An auxiliary signal a.sub.1 (t) is added to the signal x.sub.2 (t). The sum signal is converted into one-bit code words s(nT) which are multiplied in at least a first correlation channel by one-bit code words y.sub.per (kT) which are stored in a storage medium having at least N/2 addressable storage locations. The code words y.sub.per (kT) are elements of a series {y.sub.per (kT)} which is formed by the code words which occur in a predetermined time interval having a length NT and which are of a non-periodical signal of the form sign [x.sub.2 (t) + a.sub.2 (t)]. The product code words obtained are added together in an integrator. This integrator is read each time after a time interval NT and reset. The absolute value of an output code word of the integrator is optionally added to corresponding code words of other correlation channels. The sum code words obtained in this way are integrated in a second integrator whose contents is continuously compared with a detection level. If N.sub.o = .tau..sub.o /T, N is smaller than N.sub.o for example a factor of 3. The value of N determines the width of the detection characteristic.

Cross-correlation arrangement

A digital signal processing device of the recursive type, such as a recursive digital filter or a digital oscillator, comprising a storage device for storing at least one first code word related to an output code word, multiplying means for multiplying said first code word by a given weighting factor for generating a second output code word, a controlled quantizer which applies rounding or magnitude truncation upon said second code word in response to a third code word which is related to said first code word.

Digital signal processing device with quantizer

Recursive digital filter comprising at least two digital delay devices, a multiplying device having two inputs which are coupled to one another in a common branch point, a summing device from which a sum signal is derived the magnitude of which is at least equal to the sum of the output signal of the multiplying device, and a feedback circuit connected between the output of the summing device and the distribution point. The feedback circuit is provided with a discarding device which acts on numbers given in sign-and-magnitude representation and which by means of magnitude truncation restricts the number of bits of the numbers applied to the branch point.

Recursive digital filter

An apparatus for producing a predetermined transfer characteristic of information-containing signals, comprising clock means for generating a clock pulse, input means for supplying digital representations of said information-containing signals; coefficient generator means for supplying a first train of pulses of digital multiplication coefficients; delay means; digital multiplier means; and a storage device including an alternator provided with a sign reversing device and a summation device.

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Eindhoven, Netherlands

Theodoor A Claasen