Texas Instruments Corporation

Theo J Powell

Danny R Cline

Kuong Hua Hii

Yin-Chao Hwang

Wah Kit Loh

Jeffrey D Bellay

Han-Tzong Yuan

Bryan David Sheffield

Kenneth Michael Butler

Satish M Thatte

Martin D Daniels

Rashmi Sachan

Marc R Mydill

Thirumalai Sridhar

David S Ho

Jeri J Crowley

John I Hickman

Daniel R Cline

Kuong H Hii

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A ROM logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Built-in self-test arrangement for integrated circuit memory devices

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A Rom logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each having a plurality of TCAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of TCAM cells to write driver and decoding block. The data decode bypass circuit of the TCAM cell provides a raw write feature to detect faults in a full suite of memory related tests. The debug input of the data debug bypass circuit of the TCAM cell when asserted in the test mode enables the TCAM cell to write raw, unencoded data into the array, and when deasserted in the test mode, enables the testing of the TCAM array. The resulting TCAM cell provides exhaustive fault testing thereby detecting and eliminating faults in TCAM.

Array fault testing approach for TCAMs

An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.

Test enable control for built-in self-test

A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.

ROM embedded mask release number for built-in self-test

A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).

Data invert jump instruction test for built-in self-test

An integrated circuit memory device (10) is provided that has a self test monitor mode. The memory device (10) includes a memory array (26) having a plurality of memory cells. The memory device (10) further includes a built-in self test circuit (12) connected to receive a self test select signal. The built-in self test circuit (12) is operable, when the memory device (10) is in self test mode, to generate internal self test signals for operating and testing the memory array (26). A data buffer (28) is connected to receive the internal self test signals and a monitor mode signal. The data buffer (28) is operable, when the memory device (10) is in self test monitor mode, to connect the internal self test signals to terminals of the memory device (10) to provide the internal self test signals externally from the memory device (10). The monitored internal self test signals can be used to verify operation of the built-in self test circuit (12). The monitored self test signals can also be used in a tester mode to test other memory devices.

Integrated circuit memory device having built-in self test circuit with

In a built-in-self-test (BIST) unit or a memory unit, an address limits unit is provided which, prior to initiation of the test procedures, has start and stop addresses stored therein. Upon the initiation of the test procedures by the BIST unit, the start address of the address limits unit is transferred to the address counters units wherein the start address serves as the initial test address. The stop address is transferred to the address counters unit wherein the stop address will be compared with the current address. When the stop address and the current address match, the test procedure being executed by the BIST unit will be terminated. In this manner, any subarray in the memory unit can be selected for test.

Apparatus and method for subarray testing in dynamic random access

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).

Internal/external clock option for built-in self test

A system (13) is provided for structurally testing an integrated circuit device, The system includes a signature analyzer (14) operable to compress test results received from the integrated circuit device into a signature. A control device (20) is coupled to the signature analyzer (14), The control device (20) is operable to enable the compression operation of the signature analyzer (14) when the test results contain known states and disable the compression operation when the test results contain unknown states.

System and method for structurally testing integrated circuit devices

A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test. A third interface circuit is provided for an asynchronous input of data from the logic device to the coupling circuit except during test wherein the asynchronous input is isolated from the coupling circuit. A control circuit controls the third interface and the coupling circuit during test in response to an external test enable signal. In this way, the second interface is operable during test to store data in the storing circuit for input to the logic device, and the first interface transfers test results from the logic device to the storing circuit for extraction through the serial scan path.

Test circuit and scan tested logic device with isolated data lines

An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.

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Dallas, TX, United States of America

Theo J Powell