Intel Corporation

Theo Drane

Samuel Coward

Martin Langhammer

Emiliano Morini

Jordan Schmerge

George Constantinides

Examples relate to an apparatus, a device, a method, and a computer program for generating a register transfer level (RTL) representation of a circuit. The apparatus comprises processing circuitry configured to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the RTL representation of the circuit. The processing circuitry is configured to determine, for one or more operators represented by the one or more vertices of the first set of vertices of the graph, one or more logically equivalent operators. The processing circuitry is configured to include the one or more logically equivalent operators in the graph representation, such that the graph representation comprises a plurality of logically equivalent representations of the circuit. The processing circuitry is configured to generate an RTL representation of the circuit based on one of the plurality of equivalent representations of the circuit.

Apparatus, device, method, and computer program for generating a register transfer level representation of a circuit

Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.

Automatic code generation of optimized RTL via redundant code removal

Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.

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El Dorado Hills, CA, United States of America

Theo Drane