Motorola Corporation

Theo C Freund

John P Dunn

James C Nash

Tony Tong-Khay Cheng

Joseph M Harris, Ii

An integrated circuit (10) contains a central processing unit (CPU) (12) and a plurality of memory blocks (26-34) configured into one or more banks of memory. A plurality of power control switches (38-42) are used to dynamically select which of a plurality of external voltage supply signals are provided to power each of the memory blocks (26-34). The power control switches (38-42) may be configured from software via writing the data to a register (24) or can be enabled by test control circuitry (22) or can be automatically enabled in response to VDD power voltage failure. In addition, an intelligent controller can dynamically control the switches in response to execution flow of data accesses and instruction fetches from the memory banks so that only currently accessed memory banks or recently accessed memory banks are activated at a high power level while all other memory banks are in a low power stand-by mode.

Integrated circuit having standby control for memory and method thereof

A method and apparatus for viewing the contents of an internal bus (112) external to a integrated circuit (100) begins by providing a integrated circuit (100) which has the internal bus (112). Internal bus is not itself accessible to the external terminals of the integrated circuit (100). When an access on the bus (112) needs to be viewed external to the integrated circuit (100), a control section (120) forces the signals/access on the bus (112) to a second slower bus (114) within the integrated circuit (100). The second bus is coupled to circuitry (160) which is coupled to external terminals so that the external terminals can be used to inspect the contents of the bus (112) by using the bus (114) as an intermediary.

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Theo C Freund