Infineon Technologies Ag

Infineon Technologies Austria Ag

Theng Chao Long

Tian San Tan

Chau Fatt Chiang

Chan Lam Cha

Tiam Meng Pon

Petteri Palm

Swee Kah Lee

Chee Yang Ng

Kok Yau Chua

Wae Chet Yong

Josef Maerz

Sergey Yuferev

Nee Wan Khoo

Khay Chwan Saw

Jayaganasan Narayanasamy

Paul Armand Asentista Calo

Chee Hong Lee

Wei Han Koo

Andreas Kucher

Ming Kai Benny Goh

Wan Yee Ng

Kong Sin Chong

Teck Siang Hee

Jo Ean Chye

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Stacked transistor chip package with source coupling

A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

Pressure sensor having a lidless/laminate structure

A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

Multi-phase half bridge driver package and methods of manufacture

A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

Connectable package extender for semiconductor device package

A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

Semiconductor device having multiple contact clips

A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

Small footprint semiconductor package

An electronic module is provided, comprising an electronic chip arranged in the electronic module and comprising an input terminal and an output terminal; a first current path electrically connected to the input terminal; a second current path electrically connected to the output terminal; and an insulation arranged between the first current path and the second current path, wherein the first current path and the second current path extend in the same direction and arranged in close proximity to each other.

Electronic module

In one embodiment, a method of testing a semiconductor component includes loading a plurality of semiconductor components into a main turret of a turret handler, transporting the plurality of semiconductor components using the main turret to a test area, and splitting the plurality of semiconductor components into a first set and a second set. The method further includes testing a first semiconductor component in the first set at a first test pad using a tester while transporting a second semiconductor component in the second set to a second test pad and testing the second semiconductor component using the tester while transporting the first semiconductor component out of the first test pad. The first set and the second set are merged into the plurality of semiconductor components and the plurality of semiconductor components are transported away from the test area using the main turret.

Turret handlers and methods of operations thereof

A semiconductor die package includes first, second and third metal blocks insulated from one another. The first metal block has a thinner inner section, a first thicker outer section at a first end of the thinner inner section and a second thicker outer section at a second end of the thinner inner section opposing the first end. The second metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. The third metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. A semiconductor die has a first terminal attached to the thinner inner section of the first metal block, a second terminal attached to the thinner inner section of the second metal block, and a third terminal attached to the thinner inner section of the third metal block.

Semiconductor die package with multiple mounting configurations

An interposer for establishing a vertical connection between semiconductor packages includes an electrically insulating substrate having a first main side and a second main side opposite the first main side, a plurality of first electrical conductors at the first main side of the substrate, a plurality of second electrical conductors at the second main side of the substrate, and a programmable connection matrix at one or both main sides of the substrate. The programmable connection matrix includes programmable junctions configured to open or close electrical connections between different ones of the first electrical conductors and different ones of the second electrical conductors upon programming of the junctions.

Interposer with programmable matrix for realizing configurable vertical semiconductor package arrangements

A semiconductor device is provided, wherein the semiconductor device comprises a carrier, wherein the carrier comprises a first portion configured to hold a semiconductor chip; and a second portion configured for mounting the semiconductor device to a support, the second portion further comprising a first feature configured to be connected to the support; and at least one second feature configured to facilitate transfer of heat away from the first portion, wherein the at least one second feature increases a surface area of the second portion.

Semiconductor device and method of manufacturing a semiconductor device

A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable lead dimensioned for insertion into an external receptacle. The pluggable lead protrudes from the molding compound and provides a separate electrical pathway for more than one terminal of the semiconductor die. The separate electrical pathways of the pluggable lead can be provided by electrical conductors isolated from one another by electrical insulator such as molding compound or other insulation material/medium.

Growing community of inventors

Melaka, Malaysia

Theng Chao Long