Finisar Corporation

Finisar Corporaton

The'linh Nguyen

Georgios Kalogerakis

Henry Meyer Daghighian

Daniel K Case

Timothy G Moran

Jason Y Miao

Daniel Mahgerefteh

Lionel Li

Steven Gregory Troyer

Paul Kessler Rosenberg

Lewis B Aronson

Kevin John McCallion

Christopher R Cole

Luke M Ekkizogloy

Rudolf J Hofmeister

James D McVey

Andrew Carl Singer

Naresh Shanbhag

David Allouche

Juergen Hauenschild

Philip D Shapiro

Christopher Kocot

James Prettyleaf

Chris Kocot

A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

Multi-rate clock buffer

A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

Data serializer

A decision-directed phase detector (DDPD) to compare an input signal including clock and data components with a reference signal set to a clock crossover value, and generate a first compared output signal designating a transition of the input signal through the clock crossover value. The DDPD may also receive the first compared output signal and generate a phase adjustment signal, and compare the input signal with the reference signal set to a positive offset clock crossover value of the clock crossover value offset by a positive offset value, and generate a positive offset compared output signal designating a transition of the input signal through the positive offset clock crossover value. The DDPD may further generate a valid transition signal to route the phase adjustment signal to a clock generation circuit when the positive offset compared output signal transitions over a clock period.

Decision-directed phase detector

In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source.

Active linear amplifier inside transmitter module

A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

Signal conversion

In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Low power and compact area digital integrator for a digital phase detector

An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator ('PWM'). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Integrated power supply for fiber optic communication devices and subsystems

A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Integrated circuits in optical receivers

A modular device for an optical communication module configured to be coupled to an optical transmission medium. The modular device may include a first edge and a second edge and N number of electrical circuit channels between the first and second edges. Each electrical circuit channel may include at least one element configured to provide functionality for communicating optical signals through the optical transmission medium. The modular device may also have a width between the first and second edges so that each of the N number of electrical circuit channels of C number of modular devices aligns with one of P number of interface channels of an opto-electrical interface configured to be coupled to the optical transmission medium when C equals P/N and C is a whole number greater than zero.

Modular device for an optical communication module

A method of compensating for electromagnetic radiation. The method may include measuring electromagnetic radiation emanating from circuitry at a first frequency and adjusting at least one of the electrical settings of the circuitry based on the measurement of the electromagnetic radiation to reduce the electromagnetic radiation at the first frequency emanating from the circuitry.

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San Jose, CA, United States of America

The'linh Nguyen