Advanced Micro Devices Corporation

Thao H Vo

Yeng-Kaung Peng

Ying Shiau

Yung-Tao Lin

Zhi-Min Ling

Siu-May Ho

Paul M Wong

A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.

Real-time in-line defect disposition and yield forecasting system

A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the product. The computer aided design tool provides navigation to a location of interest over a layout of a wafer sample which has failed a test. The location of interest of the sample is then inspected using the dual beam scanner. The inspection may be made with either a focused ion beam scan or with a scanning electron microscope scan to provide different types of scan images and information. After inspection, a reverse engineering process (stripping back) is performed on the sample and the sample is inspected again to determine the cause of the failure of the sample. Once the cause of the failure is determined, the manufacturing process can be changed to improve the yield of the wafers.

Method of failure analysis with CAD layout navigation and FIB/SEM

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Santa Clara, CA, United States of America

Thao H Vo