Arm Limited

Thanusree Achuthan

Benoit Labbe

Yew Keong Chong

Shidhartha Das

Andy Wangkun Chen

Gus Wai-Yan Yeung

Marlin Wayne Frederick, Jr

Sriram Thyagarajan

Parameshwarappa Anand Kumar Savanth

Brian Tracy Cline

Pranay Prabhat

Xiaoqing Xu

Paul Christopher De Dood

Sahan Sajeewa Hiniduma Udugama Gamage

Philex Ming-Yan Fan

Daniel J Albers

Tom Shore

David William Granda

Yanbin Jiang

Jerry Chaoyuan Wang

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

Sylvia Xiuhui Li

Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Device and/or method for wireless signal detection

Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

Clock phase-shifting techniques in physical layout design

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

Computer implemented system and method for generating a layout of a cell defining a circuit component

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Great Cambourne, United Kingdom

Thanusree Achuthan