Intel Corporation

Thanunathan Rangarajan

Baskaran Ganesan

Mohan J Kumar

Robert Charles Swanson

Mahesh S Natu

Rajesh S Parthasarathy

Frank Binns

Gautam Doshi

Rajesh Nagaraja Murthy

Rahul Khanna

Shamanna M Datta

Minh T Le

Vinayak P Risbud

Tabassum Yasmin

Arvind A Kumar

Venkatraman Iyer

Eng Hun Ooi

Madhusudhan Rangarajan

William T Futral

Rafael De La Guardia Gonzalez

Nishi Ahuja

Robert W Cone

Anil S Keshavamurthy

Hariprasad V Nellitheertha

Deepak S

Shen Zhou

Junjie Huang

Zhijie Sheng

Richard Marian Thomaiyar

Shreesh Chhabbi

Binata Bhattacharayya

Raghavendra Y K

Shammanna M Datta

S Deepak

A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.

Memory poisoning with hints

Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.

Self-locating computing devices, systems, and methods

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

Controlling temperature of a system memory

In an embodiment, a processor includes a fuzzy thermoelectric cooling (TEC) controller to: obtain a current TEC level associated with the processor; obtain a current fan power level associated with the processor; fuzzify the current TEC level to obtain a first fuzzy fan level; fuzzify the current fan power level to obtain a second fuzzy fan level; determine a new TEC power level based at least in part on the first fuzzy fan level, the second fuzzy fan level, and a plurality of fuzzy rules; and provide the new TEC power level to a TEC device associated with the processor, where the TEC device is to transfer heat from the processor to a heat sink. Other embodiments are described and claimed.

Fuzzy logic control of thermoelectric cooling in a processor

The present disclosure is directed to a protection scheme for remotely-stored data. A system may comprise, for example, at least one device including at least one virtual machine (VM) and a trusted execution environment (TEE). The TEE may include an encryption service to encrypt or decrypt data received from the at least one VM. In one embodiment, the at least one VM may include an encryption agent to interact with interfaces in the encryption service. For example, the encryption agent may register with the encryption service, at which time an encryption key corresponding to the at least one VM may be generated. After verifying the registration of the encryption agent, the encryption service may utilize the encryption key corresponding to the at least one VM to encrypt or decrypt data received from the encryption agent. The encryption service may then return the encrypted or decrypted data to the encryption agent.

Protection scheme for remotely-stored data

Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.

Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing

Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.

Gathering sensed data from devices to manage host command transmission and cooling of the devices

Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

In an embodiment, a processor includes a thermoelectric cooling (TEC) controller to obtain a platform cooling level associated with the processor; obtain a temperature associated with the processor; calculate a TEC power level based at least in part on the platform cooling level and the temperature; and provide the TEC power level to a TEC device associated with the processor, wherein the TEC device is to transfer heat from the processor to a heat sink. Other embodiments are described and claimed.

Adaptive thermoelectric cooling in a processor

A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Fault tolerance of multi-processor system with distributed cache

Growing community of inventors

Bengaluru, India

Thanunathan Rangarajan