International Business Machines Corporation

Thanh D Trinh

Tai Anh Cao

Satyajit Dutta

Thai Q Nguyen

Lloyd Andre Walls

Nandor G Thoma

Stanley Everett Schuster

Herbert I Stoller

Byron Lee Krauter

Pee-Keong Or

Thai Quoc Nguyen

Tai Any Cao

The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Circuitry for allowing two drivers to communicate with two receivers using one transmission line

Circuitry for allowing two drivers to communicate with two receivers

A driver circuit including of one or more fingers, or parallel driver circuits, senses for an overshoot or an undershoot condition of the signal transmitted onto a transmission line coupled to the driver circuit and compensates for such an overshoot or an undershoot by temporarily turning off the offending transition portion of the driver circuit, or finger portion. This is accomplished by turning off the transistor applying one of the two supply voltages coupled to the output transmission line. Effectively, the compensation circuitry within the driver circuit more closely matches the output impedance of the driver circuit to the impedance on the driven transmission line.

Impedence self-adjusting driver circuit

The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Circuit for multiplexing a plurality of signals on one transmission line

The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.

Mixed voltage interface converter

Thin-film conductor technology is utilized to form resistors of precisely controlled value within the interior of multi-chip modules to properly terminate network circuits which interconnect one or more chips with either output pin connections or other chips on the multi-chip module. By forming and disposing the resistors within the interior of the multi-chip module, the terminating resistors may be manufactured during the multi-chip module manufacturing process. This approach preserves valuable surface area available for interconnecting the computer chips to the multi-chip module rather than consuming scarce surface area with termination resistors and other circuit elements necessary to adapt the multi-chip module and the other computer chips to each other.

Internal resistor termination in multi-chip module environments

A CMOS driver/receiver pair is provided which includes a non-inverting buffer in the input path to a differential receiver circuit. The non-inverting buffer allows a plurality of different voltages, and corresponding voltage swings, to be possible. This allows the differential receiver to compare the input voltage received from the transmission line with the output from its associated driver. Therefore, the receiver is capable of determining the voltage level (and the corresponding logic level) input from the transmission at the same time its associated driver is outputting a logic signal to another driver/receiver pair, via the transmission line. A single voltage source is utilized to provide multiple positive voltages to the differential receivers, such that differences in voltage levels which correspond to different logical combinations of '1' and '0' can be determined by the receiver.

CMOS simultaneous transmission bidirectional driver/receiver

A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

CMOS receiver circuit

The present invention includes an output circuit for a driver on a first chip that will cause an unterminated transmission line to create a predetermined voltage reflection. This reflection will then be added to the output of the driver circuit to obtain a voltage level capable of switching the receiver circuit, located on a second chip. Further, the impedance of the driver can be varied to adjust the voltage level of the signal being transmitted to the receiver, in order to reduce noise margins and cause the receiver to switch more quickly. Additionally, the transmission line impedance can also be modified to create overshoot, thereby allowing chips with dissimilar voltage levels to communicate with one another.

Communication between chips having different voltage levels

CMOS driver circuit

A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz.

High speed off-chip CMOS receiver

A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique 'pulse catcher' circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the control means to provide a three state function output. The three state static circuit provides high speed data transfer with a high drive capability full swing signal output. An enable circuit implementing four enable functions, including a testability function, is connected to the first and second pass gates to inhibit an output to the second pair of complementary FETs in the test mode. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the enable circuit to provide the three state function output, including a high impedance state.

Growing community of inventors

Austin, TX, United States of America

Thanh D Trinh