Kabushiki Kaisha Toshiba

Lsi Logic Corporation

Lsi Corporation

Rf Micro Devices, Inc.

Avago Technologies General IP (Singapore) Pte. Ltd.

Quantenna Communications, Inc.

Tzero Technologies, Inc.

2C Optics, Inc.

Thai Minh Nguyen

William Shen

Ssu-Pin Ma

Cam Luong Lu

David S Soane

Thomas B Ottoboni

Ramnath Venkatraman

Pengfei Zhang

Robert Brady Benware

Steve Chikin Lo

Arun K Gunda

Prasad Subbarao

Saket K Goyal

Young C Bae

Manjunatha Gowda

Fredric J Lim

James Ngo

Feipeng Wang

Isaac Sever

Christopher Lam

Hai H Tan

Chet Sooraparth

Kwan Chan

In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.

Closed-loop adaptive voltage scaling for integrated circuits

A technique for efficient power amplification includes providing multiple baseband signals to an amplifier. The signals may be converted to RF and combined through one or more impedance inverters.

Efficient power amplifier

A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Testing a circuit with compressed scan chain subsets

A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.

Test clocking scheme

A method and apparatus of calibrating filtering of receive and transmit signals is disclosed. The method of calibrating filtering of a received signal includes injecting an LO signal. The injected LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filtering. A desired filter tuning is determined based upon the samples and a frequency of the LO signal. The method of calibrating filtering of a transmit signal includes injecting an LO signal to a transmitter. The LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filter. A desired filter tuning is determined based upon the samples and a frequency of the LO signal.

Method and apparatus for calibrating filtering of a transceiver

A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design

A method of testing a core module includes steps of: (a) providing a core module of an integrated circuit design; (b) connecting an end user input and a core module test input to separate I/O pins of the core module to isolate logic associated with an end user signal from that associated with a core module test signal; and (c) multiplexing the end user signal and the core module test signal in the core module in response to a core module test mode signal.

Method and apparatus for testing integrated circuit core modules

Techniques to select the proper frequency band for use in a PLL from among multiple frequency bands of a multi-band VCO. The PLL comprises a detector, a loop filter, the multi-band VCO, and a control unit. The detector receives a first signal to be locked to and a second signal that is related to a VCO signal and provides a detector output. The loop filter filters the detector output to provide a control signal. The multi-band VCO selects one of the multiple frequency bands based on a select signal and provides the VCO signal at a frequency determined by the control signal. The control unit derives the select signal for the multi-band VCO based on information extracted from a third signal (e.g., a filtered version of the control signal) and a timing signal from a timer unit.

Phase-locked loop with self-selecting multi-band VCO

A wireless receiver apparatus including a voltage controller oscillator and mixer. The voltage controlled oscillator generates a first signal having a first frequency, and a second signal having the first frequency. The first and second signals are in quadrature. The mixer has a first input port for receiving the first signal, and a second input port for receiving the second signal, a third input port for receiving a third signal at a frequency centered about a third frequency. The mixer generates a fourth signal having a frequency centered about a fourth frequency which is equal to the third frequency less twice the first frequency.

Multi-phase mixer

An adaptive equalization and baseline wander correction circuit has an adaptive filter loop and an independent baseline wander correction loop by using dual halfwave rectifiers and peak detectors with capacitors to store the peak DC value of the incoming signal to be shared between the two loops.

Adaptive equalization and baseline wander correction circuit

A driver circuit is provided comprising a detection circuit, configured to sense a plurality of different variable operating condition signals, and in accordance therewith, provide a plurality of operating condition dependent output signals; a selection circuit, having a plurality of output signals, configured to receive said plurality of operating condition dependent output signals, and in accordance therewith, discretely enable, during a non-transmission state, an N number of enabled output signals; and an output circuit, having a plurality of identical segmented output modules, each of the output modules associated with a respective one of the plurality of output signals and configured to provide a respective output driving signal, wherein the output modules associated with the N number of enabled output signals each provide the output driving signal.

Tightly controlled output level CMOS-PECL driver

A low noise amplifier circuit is operable in two gain modes: high gain (approximately 15 dB) and low gain or attenuation (approximately &minus;5 dB), with a number of gain paths. In the low gain or attenuation path, the frequency response is improved by adding a diode-connected transistor and a capacitor connected in series and operating as a filter, which effectively puts a pole (p&equals;&minus;1/R,C,) in the peak of the high frequency response.

Low noise amplifier

An improved current mode driver circuit uses N-type transistors in current mirrors to achieve higher speed operation at lower cost. A pair of matched low frequency P-type transistors provide a small amount of current to each side of the differential amplifier which comprise of only N-type transistors in a current mirror connection to amplify the current supplied thereto.

Current mode driver using N-type transistors

A method is provided for applying a coating to an ophthalmic device by applying a coating to a face of the mold used to make the device and partially curing the coating, or, if the viscosity is sufficiently high, leaving the coating uncured. Then the liquid used to form the lens is poured into the mold and the liquid and coating are concurrently cured.

Growing community of inventors

San Jose, CA, United States of America

Thai Minh Nguyen