Advanced Micro Devices Corporation

Thai H Pham

Pratik Mukundray Mehta

Michael S Quimby

Bruce A Loyer

Patrick Evan Maupin

David A Spilo

A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.

Direct memory access controller with channel width configurability support

In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.

System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again

A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system

A two-level cascaded round robin arbiter. The arbiter arbitrates between a plurality of requesters for a shared resource in a round robin fashion. The arbiter comprises a series of first level arbiters which each receive a group of the plurality of requesters and select one requester in each group in a round robin manner. The first level arbiters operate in parallel to select their one requester thereby improving the overall selection time. The first level arbiters provide their selected requester to a second level arbiter which selects one group's selected requester to award use of the shared resource. The second level arbiter selects from among the groups in a round robin manner subject to an indication of a wrap condition provided by each of the first level arbiters to the second level arbiter. A wrap condition occurs when, in the process of selecting a requester, a first level arbiter has cycled from the previously selected requester through the fixed round robin order down to the lowest number requester and back up to the highest number requester. The second level arbiter continues to select the previously selected group as long as a wrap condition has not occurred in the previously selected group. Once a wrap condition has occurred, the second level arbiter selects the next group in the fixed cyclical order which has a currently active request. Each arbitration period the requester selected by the second level arbiter is latched and fed back to the first and second level arbiters which use the feedback history to select requesters according to the fixed cyclical round robin order.

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Pflugerville, TX, United States of America

Thai H Pham