Raytheon Company

Hughes Aircraft Company

Hughes Electronics Corporation

Hughes Aircraft

Thad J Genrich

Bruno A Martinez

David W Holsteen

Richard M Davis

Daniel L Spellman

Mark W Hall

An apparatus for quadrature tuner error correction includes an offset correction circuit adapted to receive a digital in-phase signal and a digital quadrature signal from a quadrature tuner. The offset correction circuit has an in-phase circuit comprising a summer adapted to receive the digital in-phase signal, subtract an in-phase offset estimate therefrom, and generate an offset corrected in-phase signal, and a feedback loop adapted to integrate the offset corrected in-phase signal, multiply the integrated offset corrected in-phase signal by a first adjustable constant, and generate the in-phase offset estimate. The offset correction circuit has a quadrature circuit comprising a summer adapted to receive the digital quadrature signal, substract a quadrature offset estimate therefrom, and generate an offset corrected quadrature signal, and a feedback loop adapted to integrate the offset corrected quadrature signal, multiply the integrated offset corrected quadrature signal by a second adjustable constant, and generate the quadrature offset estimate.

Apparatus and method for quadrature tuner error correction

A digital tuner for maximizing tuning range for a particular intermediate frequency includes an analog to digital converter ( ) operating at an input clock frequency to sample an analog input signal ( ) and output a multi-bit digital word for each sample, a demultiplexer ( ) in communication with the analog to digital converter ( ) and a plurality of mixers ( ) to convert serial samples from the analog to digital converter ( ) to parallel samples for input to the mixers ( ) functioning as quadrature multipliers, local oscillators ( ) in communication with corresponding ones of the mixers ( ), and a parallel cascaded integrator comb filter ( ) in communication with the mixers ( ) for filtering and decimating the parallel samples, where the mixers ( ), the local oscillators ( ), and the filter ( ) operate at a frequency having adjacent harmonics substantially centered about the intermediate frequency. A method for determining an operating frequency for a digital tuner having an associated intermediate frequency to reduce clock harmonic interference includes determining a maximum frequency based on operating parameters of tuner elements, selecting a harmonic of the operating frequency based on the intermediate frequency and the maximum frequency, and selecting the operating frequency based on the intermediate frequency.

Digital tuner with optimized clock frequency and integrated parallel CIC filter and local oscillator

A method for generating a trigonometric function is provided that includes an input angle being received and automatically separated into a first component angle and a second component angle. A sine value for the input angle is automatically determined based upon the first and second component angles. A cosine value for the input angle is automatically determined based upon the first and second component angles. The trigonometric function is automatically generated based upon the sine and cosine values for the input angle.

Method and system for generating a trigonometric function

A parallel asynchronous sample rate reducer ( ) for converting a synchronous parallel digital input signal (INP_DAT) into a parallel digital output signal (OUT_DAT) having an average aggregate sample rate that is asynchronous with respect to the input sample clock rate. The sample rate reducer ( ) includes a parallel phase accumulator ( ) for determining the output sample number values and the fractional phase values corresponding to each output sample number combined in an output value (PHS_ACC). Control logic ( ) receives the phase accumulator output value PHS_ACC and generates an interpolator value (CTL_INT) for controlling interpolation of the input data to interpolate the data to the predetermined output sample number and the corresponding fractional phase values. The control logic ( ) also generates control a build value (CTL_BLD) to enable alignment of the interpolated data signals. A parallel interpolator ( ) receives the input samples and the interpolator control value (CTL_INT) to generate a parallel interpreted data signal (PAR_INT) of the samples. A parallel word builder ( ) then erases invalid samples and compresses samples to the output data word (OUT_DAT) of consecutive, valid samples.

Parallel asynchronous sample rate reducer

Apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit converts the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit is coupled to the digital-to-analog converter. The RF/analog circuit includes a voltage controlled oscillator to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator generates an in-phase tuner output and a quadrature tuner output in response to the modulated output signal. An analog-to-digital converter is coupled to the quadrature tuner and converts the in-phase tuner output and the quadrature tuner output to digital in-phase and quadrature tuner outputs. The digital in-phase tuner output and the quadrature tuner output are fed back to the digital circuit to generate the digital modulation control signal.

Apparatus and method for phase and frequency digital modulation

A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (,) mounted on a mezzanine board (,) to provide functional flexibility and not requiring an additional slot in a computer chassis. In a preferred embodiment, the module is utilized to process weather information and performs the functions of demodulation, bit and frame synchronization, and FIFO buffer control. The gate arrays may be reprogrammed to implement either AM demodulation or BPSK demodulation or adapted to process other types of information, such as telemetry information.

Configurable interface module

A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (44, 46, 48) mounted on a mezzanine board (30) to provide functional flexibility and not requiring an additional slot in a computer chassis. In a preferred embodiment, the module is utilized to process weather information and performs the functions of demodulation, bit and frame synchronization, and FIFO buffer control. The gate arrays may be reprogrammed to implement either AM demodulation or BPSK demodulation or adapted to process other types of information, such as telemetry information.

Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substantially wide bandwidth to output demultiplexed data signals at a lower clock rate. A digital signal processor processes the demultiplexed data signals to produce detected signals. A plurality of algorithms are implemented in the demodulator and bit synchronizer that include Costas loop demodulators, for example implemented using a carrier loop/lock detector, a direct digital synthesizer and a plurality of multipliers. Eight-tap T/2 baseband equalizers are implemented using in-phase and quadrature-phase accumulators and equalizers, and an in-phase/mid-phase bit synchronizer is implemented using the in-phase accumulator and a mid-phase accumulator and equalizer. The implementation is unique in that most of the signals are demultiplexed to allow parallel processing.

High data rate digital demodulator and bit synchronizer

The automatic gain control loop has an automatic gain control loop filter generating a multi-bit gain control word in response to the power level of the output signal of the loop. A shifter circuit shifts the input data by selected number of bits under the control of selected most significant bits of the gain control word multiplying the power of the input signal. A multiplier circuit multiplies the shifted data output from the shifter circuit by predetermined multiplication factors under the control of the remaining bits of the gain control word. The shifting and adding of the input data under the control of the gain control word maintains the power level of the output signal within a predetermined range.

Digital signal processing automatic gain control amplifier

A high speed digital filter for use in digital interpolation and decimation provides a parallel processing implementation for integrator stages of a cascaded integrator-comb (CIC) filter. The parallel structure of the present invention is easily cascadeable since it allows subsequent integrator stages access to intermediate samples generated by preceding integrator stages. The parallel integrator structure may be implemented directly or may be reduced in complexity by removing redundant logic for use in decimator output sections or interpolator input sections. The parallel implementation of a CIC filter allows much higher sample rate filtering to be implemented with fewer standard CMOS logic devices than currently recognized implementations.

Parallel cascaded integrator-comb filter

A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.

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Aurora, CO, United States of America

Thad J Genrich