Cadence Design Systems, Inc.

Digeo, Inc.

Thad Clay McCracken

Mark Peting

Wei-Jin Dai

Ping-Chih Wu

Lung-Chun Liu

Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Method and system for implementing electronic design entry

The invention provides an efficient structure for synthesized static arrays. Array structures are very common in chip design, and often when doing ASIC design the option of custom-designing these arrays does not exist, therefore necessitating that the arrays be synthesized, placed and routed on silicon in a manner similar to random logic. Standard array structures are not easily synthesized, placed and routed. The invention takes advantage of the case in which the design requirements are such that the array is loaded in whole and then remains static for a period of time. The array implementation writes one column of the array (instead of a row) at a time so that the desired contents of the array are &ldquo;rotated&rdquo; 90 degrees before being written to the array. This allows the latches in a column to share a gated clock signal, which allows for an array placement optimized for clock distribution and for general routing density.

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Portland, OR, United States of America

Thad Clay McCracken