Xilinx, Inc.

Thach-Kinh Le

Carl H Carmichael

Conrad A Theron

Donald H St Pierre, Jr

Arun K Mandhania

Chakravarthy K Allamsetty

A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.

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Monte Sereno, CA, United States of America

Thach-Kinh Le