Nvidia Corporation

Lsi Corporation

Tezaswi Raja

Wen Yueh

Siddharth Saxena

Stephen Felix

Nishit Harshad Shah

Brian Lawrence Smith

Fei Li

Suhas Satheesh

Prashant Singh

Gunaseelan Ponnuvel

Abhishek B Akkur

Kalyana Bollapalli

Krishnamraju Kurra

Sagheer Ahmad

Ephrem C Wu

Sachin Satish Idgunji

Roman Surgutchik

Ting Ku

Madhu Swarna

Divya Ramakrishnan

Robin J Tang

Jesse Max Guss

Suhas Mysore Satheesh

Andy Charnas

Miguel Rodriguez

Kedar Rajpathak

Kartik Joshi

Vinayak Bhargav Srinath

Ben Faulkner

Sanjay Pant

Ting Zhou

Tao Liu

Rajeshwaran Selvanesan

Benjamin Faulkner

George Ferenc Kokai

Vikram Mehta

Kevin Wilder

Chad Plummer

Aniket Naik

Jun Gu

Kevin Ye

Javid Aziz

Chengcheng Liu

Gaurav Ajwani

Shalimar Rasheed

Ram Kumar Ranjith Kumar

Miloni Mehta

Jiale Liang

Kerwin Fu

Seyed Nima Mozaffari Mojaveri

Kevin Zhou

Charlie Hwang

Chinmay Apte

Jeffery Bond

Ayon Dey

Andrew Charnas

Divyesh Shah

Fei (Walter) Li

Raj Jayakar

Veeramani V

Daniel Rodriguez

Andy Chamas

Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

Technique for enabling on-die noise measurement during ate testing and IST

Circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. The method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.

Low power and area clock monitoring circuit using ring delay arrangement for clock signal having phase-to-phase variation

Techniques are described for detecting an electromagnetic ('EM') fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.

Detection of electromagnetic fault injection attacks on digital systems

An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.

On die current sink circuit for overshoot mitigation

Circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer. In one embodiment, the method includes sinking or sourcing current through a selected on of a plurality of devices under test (DUTs) on the semiconductor wafer, converting the current sourcing or sinking into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. In one embodiment, the duty cycle of the output clock is dependent on the current sinking or sourcing through the selected at least one of the plurality of DUTs on the wafer and electrical characteristics of material local to the specific area of the wafer where the selected one of the plurality of DUTs is located are determined based on the duty cycle of the output clock.

Integrated current monitor

Circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer is disclosed. In one embodiment, an IC is disclosed that comprises at least one processing subsystem and at least one integrated common current monitor (ICCM) located within the processing subsystem(s). In one embodiment, the ICCM includes current-to-voltage conversion circuitry that converts a current throughput (I) of a selected at least one of the plurality of DUTs to a corresponding voltage for a plurality of regulated drain-to-source voltages (V) across the selected DUT(s). In one embodiment, the ICCM is configured to determine a duty cycle of a voltage that corresponds to the Iand Irepresents electrical characteristics of material local to an area of a semiconductor wafer specific to a location where the ICCM is located.

Integrated current monitor using variable drain-to-source voltages

Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.

Transient current-mode signaling scheme for on-chip interconnect fabrics

The disclosure provides a voltage detecting circuit that detects voltage increases and voltage decreases using a diode drop and voltage thresholds. The voltage detecting circuit, referred to as a voltage variation detector, uses the diode to maintain a differential between the voltage being monitored and a voltage threshold. When the diode is reversed bias, the voltage variation detector generates a detecting signal indicating the monitored voltage crossed the voltage threshold. In one example a voltage variation detector is disclosed that includes: (1) a transistor stack that corresponds to a voltage threshold, (2) a transistor diode, and (3) an inverter that receives an input signal and provides an detection signal that controls one or more gates of the transistor stack, wherein the transistor stack and the transistor diode provide the input signal and the detection signal indicates when the voltage crosses the voltage threshold.

Overvoltage and undervoltage detector

Circuitry and a method of operating a clock monitoring circuit for monitoring a clock signal is disclosed. The method comprises charging a first capacitor connected to a connection between a first pair of transistors and a voltage reference, charging a second capacitor connected to a connection between a second pair of transistors and to the voltage reference, sinking a current from the first and second pair of transistors with a constant current sink, and asserting a clock slow detect (CSD) signal when a voltage at the constant current sink drops below a threshold indicating durations of phases of the clock signal lengthen.

Low power and area clock monitoring circuit using a capacitor and constant current sink

Silicon test structures are described that enable separate measurement of n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) transistor delays. NMOS and PMOS specific non-inverting stages may be used to construct a multi-stage ring oscillator. Each of the non-inverting stages generates either a rising or falling primary transition that is determined by either NMOS or PMOS transistors, respectively. The opposing transition for a particular non-inverting stage is triggered by propagation of the primary transition to a subsequent non-inverting stage (producing a 'reset' pulse). A frequency of the ring oscillator is determined by the primary transition and one transistor type (NMOS or PMOS). Specifically, the frequency is determined by the propagation delay of the primary transition through the entire ring oscillator.

Silicon test structures for separate measurement of NMOS and PMOS transistor delays

A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

Circuit structures to measure flip-flop timing characteristics

Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

Distributed digital low-dropout voltage micro regulator

In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.

On-die techniques for asynchnorously comparing voltages

In various embodiments, a current measurement circuit measures an input current within an integrated circuit. The current measurement circuit includes an integration capacitor, an operational amplifier, a comparison capacitor, an inverter, and multiple switches. The current measurement circuit is coupled to a clocking circuit that, during operation, generates a two-phase clock having a frequency that is proportional to the input current. At least a portion of the switches are turned on during a first phase of the two-phase clock and are turned off during a second phase of the two-phase clock.

On-die techniques for converting currents to frequencies

Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

Techniques for configuring a processor to execute instructions efficiently

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San Jose, CA, United States of America

Tezaswi Raja