Fujitsu Corporation

Tetsuya Yoshida

Yoshihiko Koike

Naoya Watanabe

Kenji Yoshida

Shuji Yoshida

Norihiro Nakatsuhama

Tomohide Yamamoto

Yoshiaki Nagatomi

Kenichi Kawabata

Masayoshi Kusumoto

Tomohiro Wada

By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

Marginless status determination circuit

A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal and the second power supply terminal to produce at an output node thereof a signal responsive to a difference between a potential of the first power supply terminal and a potential of the second power supply terminal, and a core circuit coupled to the output node of the comparison circuit to perform a test operation in response to the signal.

Semiconductor device and entry into test mode without use of unnecessary terminal

First and second latch circuits store '0' and '1', respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is &#x201c;1&#x201d;, and outputs &#x201c;0&#x201d; when the output signal from the second latch circuit is &#x201c;0&#x201d;. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is &#x201c;1&#x201d;. When the register setting data indicates &#x201c;0&#x201d;, the output signals from both the first and the second latch circuits become &#x201c;0&#x201d;, and until being reset, the write error protect state is maintained.

Memory control circuit, memory device, and microcomputer

A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part in a third wiring layer are connected by a second connecting part. A fourth wiring part continuously connected with the third wiring part and a fifth wiring part in the second wiring layer are connected by a third connecting part. The fifth wiring part and a sixth wiring part in the first wiring layer are connected by a fourth connecting part. A conducting path that is continuously connected from the starting terminal to an output end is formed by connecting a mound-shaped conducting path thus formed.

Semiconductor device

A semiconductor device that prevents malfunction in an external circuit by preventing an indefinite signal from being output at the time of power being applied. A processing circuit is supplied with an internal power supply voltage from an internal power supply voltage generating circuit and performs a predetermined process. An output circuit outputs the result of processing by the processing circuit. When the supply of an external power supply voltage is begun, a control circuit exercises control so that output from the output circuit will be kept in a predetermined state. A supply circuit supplies an external power supply voltage to the control circuit.

Growing community of inventors

Kawasaki, Japan

Tetsuya Yoshida