Hitachi, Ltd.

Nec Corporation

Sanyo Denki Co., Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Hitachi Displays, Ltd.

Hitachi Consumer Electronics Co., Ltd.

Tetsuya Yamazaki

Kousuke Takahashi

Hidetaka Shigi

Yasuhiro Yoshitake

Fusaji Shoji

Haruhiko Matsuyama

Toshiharu Miwa

Jun Tanaka

Shigeyuki Nishitani

Takashi Inoue

Hitoshi Yokono

Shoichi Uchino

Kiyoshige Kinugawa

Susumu Sasaki

Naoki Matsushima

Naoya Kanda

Eiji Matsuzaki

Makoto Okai

Koji Suzuki

Tomio Yaguchi

Nobuaki Hayashi

Fumio Kataoka

Hideo Sotokawa

Masashi Nishiki

Takahisa Toda

Hiroaki Okudaira

Yukio Maeda

Takehiko Hasebe

Takahiko Muneyoshi

Akiko Iwata

Naoya Kitamura

Masayuki Kyooi

Ryuichi Takahashi

Takayoshi Sowa

Mitsuo Yoshimoto

Shirou Akamatsu

Shogi Ikeda

Miharu Otani

Takashi Kashimura

A product specification setting apparatus includes: an electronic tag for updatably storing specifications of a product; and a control computer for controlling the product according to the stored specifications. A fan motor includes: a motor driving unit for driving a motor for rotating a fan; an electronic tag for updatably storing specifications of the fan motor; and a control computer for controlling the motor driving unit according to the stored specifications.

Product specification setting apparatus and fan motor having the same

A wire fixture for fixing an electric wire in a wire mounting hole formed in a panel includes: a fixing member to be wound and fixed around the electric wire; a first cable bushing including a first main body portion to be attached to the electric wire from one side in a radial direction; and a second cable bushing including a second main body portion to be attached to the electric wire from the other side in the radial direction. The first and second cable bushings each include a locking member that extends in one direction from each of the first and second main body portions in a longitudinal direction of the electric wire to lock the fixing member.

Wire fixture

A highly reliable LED package mounting structure which can realize improvement in solder fatigue life at low costs is provided. An LED package has a light-emitting surface which is perpendicular to a mounting surface of a circuit board, comprises connection terminal portions on the side face or on the side face and the bottom face of the package, and is joined with the circuit board by soldering via the connection terminal portion. Furthermore, the shape of the solder is optimized by defining the relative position relation between the end of an electrode on the central side of the LED package on the bottom face of an LED package body and the end of a component mounting pad on the circuit board.

LED package and LED package mounting structure

In an image display apparatus using an FED or an organic EL element, image display that is high in illumination uniformity and high in image quality can be performed. A display element with a matrix structure which conducts linear sequential driving which determines the luminance by a current is used, a threshold voltage of a cathode line immediately before one select period has been terminated where a control electrode line is sequentially driven is measured by a threshold voltage measuring section, the measured threshold voltage is recorded for each of the pixels, and a driving signal at the time of selecting the pixel is corrected by using the value of the recorded threshold voltage, to thereby control electric charge that is emitted from a cathode.

Flat panel display apparatus

In lithographic (exposure) processing for semiconductor device fabrication, the task of extracting exposure parameters is performed by calculating exposure energy and focus offset using a test wafer for each exposure device, because fluctuations due to differences between exposure devices are large. For the fabrication of semiconductor devices in multiple-product small-lot production, the number of times the task of extracting exposure parameters has to be performed increases, so that the operation ratio of the exposure devices decreases, and the TAT of the semiconductor device fabrication increases. Moreover, as the miniaturization of semiconductor devices advances, differences between the exposure devices cause defects due to the exposure processing, and the yield of the semiconductor device fabrication decreases. In an improved method of exposure processing for semiconductor devices, the exposure energy and focus offset according to the illumination parameters for an exposure device and optical projection system, using information regarding the projection lens aberrations of a plurality of exposure devices, the photoresist parameters, and the circuit pattern information, as determined beforehand, are calculated using an optical development simulator, and the exposure processing is carried out using an exposure device, selected from a plurality of exposure devices, in which the process window is within a certain tolerance value.

Exposure processing method and exposure system for the same

Exposure method

A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the respective second windows.

Multi-layer wiring substrate and manufacturing method thereof

The present invention provides the wiring structure having a wiring layer and insulation layer and the method of manufacturing the same, wherein at least a part of the wiring of said wiring layer comprises copper, and said insulation layer comprises the polyimide obtained by heating the polyimide precursor composition containing the polyimide precursor having the repeating unit which can be represented by the following general formula (Chemical formula 15). ##STR1## (In this formula, R.sup.1 is at least one type of quadrivalent organic group selected from among the Chemical formulae 16, while R.sup.2 is a bivalent organic group containing aromatic ring).

Wiring structures and method of manufacturing the same

In a token train retrieval device including a memory device (24) for memorizing a plurality of tokens each of which starts at a starting address and ends at an end address and each of which has a nest level selected from a plurality of nest levels and comprises a header and a data set where header comprises a data length code and a data identifier code including a nest bit, a retrieval condition memory (25) memorizes a retrieval condition including a plurality of designated nest level codes and a plurality of designated identifier codes. A header register (26) holds the data length code, the data identifier code, and the nest bit as a held data length code, a held data identifier code, and a held nest bit. Responsive to the held data length code, a supplied header, and a decided nest level code, a checking circuit (27) produces a matching signal when the retrieval condition is satisfied. An intra-train address generating circuit (29) generates an intra-train address variable in accordance with the matching signal and the held data length code. Supplied with the intra-train address and the held data length code, an end address calculating circuit (30) calculates the end address of each token as a calculated address. Responsive to the intra-train address, the calculated address, and the held nest bit, a nest level decision circuit (31) supplies the checking circuit with the decided nest level code indicative of one of the nest levels.

Token train retrieval device for simultaneously determining nest level

In a token train retrieval device including a memory device (24) for memorizing a plurality of tokens as stored tokens each of which starts at a starting address and ends at an end address and each of which has a nest level selected from first through N-th nest levels and comprises a header and a data set where the header comprises a data length code and a data identifier code including a nest bit, a retrieval condition memory (25) memorizes a retrieval condition as a stored condition. Supplied with the header, a header register (26) holds the data length code, the data identifier code, and the nest bit as a held data length code, a held data identifier code, and a held nest bit. Responsive to the held data identifier code and a decided nest level, a checking circuit (27) checks whether or not the stored condition is satisfied to produce a matching signal when the stored condition is satisfied. An intra-train address generating circuit (29) generates an intra-train address variable in response to the matching signal, the held nest bit, and the held data length code. By using the intra-train address and the held data length code, an end address calculating circuit (30) calculates the end address of each token as a calculated address. By using the calculated address, the intra-train addresses, and the held nest bit, a nest level decision circuit (31) decides the decided nest level indicative of one of the first through the N-th nest levels.

System for retrieving token having a selected nest level and satisfying

When a nest level judging device is supplied with tokens each of which has a nest level selected from first through N-th nest levels as a selected level and each of which comprises a header and a data set where the header comprises a data length code and a data identifier code including a nest bit, a counter (31) produces an address signal for specifying starting and end addresses of each of the tokens and a varying address varying from the starting address to the end address. Supplied with the header, a header register (32) produces a data length signal representative of the data length code and a nest bit signal which represents that the each of the tokens is nested in the data set thereof. Supplied with the address signal and the data length signal, an end address calculator (33) calculates the end address of the respective tokens and produces an end address signal representative of the end address. Responsive to selection signals, a selector (34) delivers the end addresses of the respective tokens as first through N-th end addresses. Supplied with the nest bit signal, the address signal, and the first through the N-th end addresses, a decision unit (35) decides a decided nest level, indicative of one of the first through the N-th nest levels that is selected as the selected level. The level decision unit delivers the decided nest level as one of the selection signals to the selector.

Nest level judging device for judging the starting and the end addresses

A multilayer wiring substrate having high reliability can be produced in good productivity by subjecting metal wiring layers to stabilization treatment on the surface with a metal such as Cr, Mo or the like or an aqueous solution of water glass so as to prevent generation of hillocks or whiskers and to improve chemical resistance.

Multilayer wiring substrate and production thereof

The present invention relates to an element comprising a superconductive material or a wiring formation technique. In a thin film wiring board in which a superconductive material is used as a conductor, annealing should be conducted at a high temperature in an oxygen atmosphere after formation of a film in order to convert the conductor portion into a superconductive material, which makes it necessary to use an inorganic oxide as the insulating film. This brought about a problem that the etching of the second and subsequent insulation layers causes a damage to the wiring and insulation layer provided thereunder. In the present invention, an over-etching preventing layer is provided on a wiring layer provided under the second and subsequent insulation layers in order to solve the problem in question. The present invention brings about an effect of realizing the formation of a multi-layered wiring layer by making use of a superconductive material.

Process for preparing superconductive wiring board

Growing community of inventors

Tokyo, Japan

Tetsuya Yamazaki