Kabushiki Kaisha Toshiba

Nippon Telegraph and Telephone Corporation

Tetsuya Yamaguchi

Hisanori Ihara

Hirofumi Yamashita

Ikuko Inoue

Hidetoshi Nozaki

Hiroshige Goto

Nagataka Tanaka

Nobuo Nakamura

Akira Ono

Naoyuki Shigyo

Hiroshi Naruse

Hidenori Shibata

Akiko Nomachi

Yoshiyuki Shioyama

Masato Ono

Hideki Inokuma

Takahide Hoshide

Keisuke Hasegawa

Masako Hori

Koji Namba

Akira Makabe

Seigo Abe

Ryohei Miyagawa

Yoshinori Iida

Michio Sasaki

Hiroaki Ishiwata

Akiko Mori

Keiji Mabuchi

Yoshitaka Egawa

Akihiko Furukawa

Takaaki Kamimura

Naoki Wakita

Eiji Oba

Masayuki Ayabe

Shogo Furuya

An influence on object expression performed at a transmission destination is reduced. A position information reception unitof an information integration devicereceives, regarding objects which are measured by a plurality of sensors from a plurality of locations and overlap in any of the locations, position information for each location on areas of the objects. A position information integration unitcalculates smallest rectangles or largest rectangles surrounding the objects by using the position information for each location.

Information integration method, information integration device, and information integration program

The present invention is to improve accuracy of position information of an object. A labeling unitof an information integration deviceassociates a label included in tracking data with an object area having a largest ratio of overlapping areas overlapping label areas included in the tracking data with regard to the object area or an object area having a largest size of overlapping areas overlapping label areas included in the tracking data, among a plurality of object areas included in a Depth map.

Matching timings of transmitting pieces of information for reproducing video and audio with presence and handling loss are provided. An information synchronization device is configured to synchronize, to a reference timestamp, data in which one or more labels for identifying respective one or more subjects on a video and one or more pieces of location information for identifying respective locations of the one or more subjects are respectively associated. The information synchronization device includes a reception unit for receiving the data at each time, a buffer for storing the received data, and a location information interpolation unit for generating, when pieces of the location information at times before and after the reference timestamp is stored into the buffer for any of the labels, location information of the label at the reference timestamp by interpolation using the pieces of the location information.

Information synchronization device, information synchronization method, and information synchronization program

According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.

Solid-state imaging device

According to one embodiment, a solid-state imaging device includes a diffusion layer, first and second diffusion layers, and p-type amorphous silicon compound. The diffusion layer of a first conduction type is formed in a surface of a semiconductor substrate of the first conduction type. The diffusion layer functions as a charge accumulation part for accumulating electrons generated in the semiconductor substrate by light emitted from a back side of the semiconductor substrate to a surface side. The first and second diffusion layers of a second conduction type sandwich the charge accumulation part and are formed so as to reach the inside of the semiconductor substrate from the surface of the semiconductor substrate. The p-type amorphous silicon compound electrically isolates the charge accumulation part and is buried in the first and second trenches formed on the back side of the semiconductor substrate.

Solid-state imaging device and method of manufacturing the same

According to one embodiment, a back side illumination solid-state image sensing device which comprises a pixel region where a plurality of pixels each including a photoelectric converter and a signal scanning circuit are arranged on a semiconductor substrate, and in which a light illumination surface is formed on a substrate surface opposite to a surface of the semiconductor substrate on which the signal scanning circuit is formed, includes a silicon oxide film formed on the semiconductor substrate on the light illumination surface side, a p-type amorphous silicon compound layer formed on the silicon oxide film, and a hole storage layer formed by the p-type amorphous silicon compound layer near an interface between the semiconductor substrate on the light illumination surface side and the silicon oxide film.

Solid-state image sensing device and method of manufacturing the same

A solid-state image sensor includes a semiconductor layer having a first conductive type, diffusion layers which are arranged in the semiconductor layer, each having a second conductive type, and each includes a pixel, a pixel transistor disposed on the semiconductor layer, and an insulating layer which is disposed under the pixel transistor and which is not disposed under the diffusion layers. The pixel transistor is disposed between the other pixels different from the pixel being electrically connected to the pixel transistor.

Solid-state image sensor with reduced signal noise

Each of the unit cells provided on a semiconductor substrate of a solid-state imaging device comprises a first p-type well which isolates the semiconductor substrate into an n-type photoelectric conversion region, a second p-type well which is formed in the surface of the photoelectric conversion region and in which a signal scanning circuit section is formed, and a signal storage section which is comprised of a highly doped n-type layer which is formed in the surface of the photoelectric conversion region apart from the second p-type well and higher in impurity concentration than the photoelectric conversion region. The signal storage section having its part placed under a signal readout gate adapted to transfer a packet of signal charge from the storage section to the signal scanning circuit section and its part at which the potential becomes deepest located under the readout gate.

Solid-state imaging device comprising a signal storage section including a highly doped area

An n/p/psubstrate where a p-type epitaxial layer and an n-type epitaxial layer have been deposited on a p-type substrate is provided. In the surface region of the n-type epitaxial layer, the n-type region of a photoelectric conversion part has been formed. Furthermore, a barrier layer composed of a p-type semiconductor region has been formed so as to enclose the n-type region of the photoelectric conversion part in a plane and reach the p-type epitaxial layer from the substrate surface. A p-type semiconductor region has also been formed at a chip cutting part for dividing the substrate into individual devices so as to reach the p-type epitaxial layer from the substrate surface.

A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio &#x394;C/C or a resistance-by-capacitance variation ratio &#x394;(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (&#x3b4;) for the wiring structure, a tolerance (&#x3be;) for the capacitance variation ratio (&#x394;C/C), and a tolerance (&#x3be;) for the resistance-by-capacitance variation ratio (&#x394;(RC)/(RC)), evaluates a fringe capacitance ratio (F=C/C) according to a fringe capacitance Cand parallel-plate capacitance Cof the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following:  The method employs an equivalent-variations condition defined as |&#x394;C/C|=|&#x394;(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

Method of designing wiring structure of semiconductor device and wiring structure designed accordingly

A solid-state image pickup device includes a semiconductor substrate including a substrate main body having P-type impurities and a first N-type semiconductor layer provided on the substrate main body, an image pickup area including a plurality of photoelectric converters in which the plurality of photoelectric converters include second N-type semiconductor layers, the second N-type semiconductor layers being provided on a surface portion of the first N-type semiconductor layer independently of one another, and a first peripheral circuit area including a first P-type semiconductor layer formed on the first N-type semiconductor layer. The solid-state image pickup device further includes a second peripheral circuit area including a second P-type semiconductor layer formed on the first N-type semiconductor layer and connected to the substrate main body.

[object Object]

According to an aspect of the invention, there is provided an amplification-type solid-state image sensing device which uses a semiconductor substrate formed by epitaxially depositing an n-type semiconductor layer on a p-type semiconductor substrate and has a photoelectric conversion unit formed in the n-type semiconductor layer including a first p-type semiconductor layer which is formed under the photoelectric conversion unit of at least one of a G pixel portion and a B pixel portion a second p-type semiconductor layer which is formed to surround the photoelectric conversion unit together with the first p-type semiconductor layer and has a depth up to the first p-type semiconductor layer and a third p-type semiconductor layer which is formed to surround an R pixel portion and has a depth up to the p-type semiconductor substrate.

Amplification-type solid-state image sensing device

A solid-state image pickup device comprising a semiconductor substrate which comprises a substrate body containing P-type impurities and a first N-type semiconductor layer containing N-type impurities, the first N-type semiconductor layer being provided on the substrate body, and including a first P-type semiconductor layer which contains p-type impurities, and which is located on the substrate body, a plurality of optical/electrical conversion portions formed of second N-type semiconductor layers which are provided independently of each other in respective positions in a surface portion of the first N-type semiconductor layer, and a plurality of second P-type semiconductor layers which are formed to surround the optical/electrical conversion portions, which are provided along element isolation regions provided in respective positions in the surface portion of the first N-type semiconductor layer, and which continuously extend from the surface portion of the first N-type semiconductor layer to a surface portion of the first P-type semiconductor layer.

Solid-state image pickup device and method of manufacturing the same

A solid state imaging device includes a substrate of a first conductivity type. A transistor, which includes a first gate electrode and a first and second impurity areas, is provided on a surface of the substrate. The first and second impurity areas are formed in the surface of the substrate and sandwich a region under the first gate electrode. A third impurity area of a second conductivity type is formed in the surface of the substrate and spaced from the second impurity area at an opposite side to the first gate electrode. A fourth impurity area is formed under the second impurity area and connected to the third impurity area. A second gate electrode is provided above the substrate. A fifth impurity area of the second conductivity type is formed in the surface of the substrate. The third and fifth impurity areas sandwich a region under the second gate electrode.

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Tokyo, Japan

Tetsuya Yamaguchi