Nec Corporation

Sony Corporation

Tetsuya Uemura

Hiroyuki Takahashi

Satoshi Yamamoto

Yasufumi Suzuki

Toshio Baba

Kenji Tsushio

Chihiro Motono

Simon Currie

An information processing apparatus has a plurality of recording media, and includes an imaging unit operable to capture an image of a subject, and a recording unit operable to record image data of the captured image onto the recording media such that the amounts of recorded image data differ between the recording media. The same image data is recorded onto at least a first recording medium built in the apparatus and a second recording medium removable from the apparatus such that the amount of data recorded on the first medium is smaller than that recorded on the second medium. In this information processing apparatus, a user can view images captured previously with more ease because image data recorded on the first recording medium is sorted by date and is provided to the user in this state.

Information processing apparatus and method, and program

A memory cell is formed by an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and a second power supply.

Memory device

A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.

Differential negative resistance HBT and process for fabricating the same

The present invention includes: a series circuit which has a negative differential resistance element and another negative differential resistance element that has a control terminal capable of controlling a value of an element current; a transfer gate; a latch circuit which has negative differential resistance elements connected in series; and an inverter circuit which has an FET as a drive element and a negative differential resistance element as a load element. With this, such a flip-flop can be obtained that when a clock signal is applied to a power supply terminal of the series circuit and a control terminal of the transfer gate and an input signal is supplied to the control terminal of the negative differential resistance element, an output is placed at a terminal.

Flip-flop circuit

The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors. Due to the construction, even when the gate voltage is 0, electrons or positive holes are induced in the surface of the second semiconductor, and a tunnel current can be flowed between the source and the drain. Since control of the tunnel current can then be preformed by applying a reverse bias voltage between the gate and the drain, the leak current of the gate can be suppressed.

Tunnel transistor and method of manufacturing same

A tunneling transistor comprising an emitter layer, a barrier layer having a conduction band higher in energy than a conduction band of said emitter layer and a valence band lower in energy than a valence band of said emitter layer, and further having a thickness with which electrons can substantially tunnel the barrier layer, a collector layer having a conduction band lower in energy than the valence band of said emitter layer and a conductivity type opposite to said emitter layer, and further having a thickness with which quantum levels are substantially formed, a gate layer having a conduction band higher in energy than the conduction band of said layer and a valence band of said emitter layer, and further having a thickness with which the probability of electron tunneling is substantially greatly reduced, said layers been laminated in this order, and electrodes which form ohmic junctions on said emitter layer and said collector layer and an electrode which forms a Schottky junction on said gate layer.

Growing community of inventors

Tokyo, Japan

Tetsuya Uemura