Nec Corporation

Mitsubishi Electric Corporation

Nof Corporation

National Institute of Infectious Diseases

Saitama Medical University

Hoya Corporation

Other

Renesas Electronics Corporation

Hokkaido University

Roki Techno Co., Ltd.

Tetsuya Uchida

Kenichi Morokuma

Kiyohiro Saito

Tatsuo Nishimoto

Jun Tomisawa

Kenji Tanagawa

Masanori Matsui

Hiroshi Oda

Maiko Taneichi

Hideo Sugimoto

Shoji Yoshida

Takashi Takeuchi

Norio Ishitsuka

Atsushi Maeda

Hiroshi Ishida

Tomoyuki Tada

Kazuyasu Nishikawa

Yasuhiro Kimura

Masaki Mikami

Shoichi Orita

Shoichi Yokoyama

Natsuo Yamaguchi

Yukio Ishikawa

Shuji Kakimoto

Takayoshi Kishimoto

Hideyuki Kanai

Motokazu Sekine

Ai Mikuma

Masahiko Shima

Hirofumi Kawagoe

Mari Okazaki

Toshitaka Akatsuka

Kiichi Kajino

Minoru Abiko

Takehiko Kijima

Masatoshi Akihara

Tomoko Koda

Toshiya Fukuda

The filter vessel attachment/detachment apparatus includes a first conduit end, wherein a first conduit for the fluid to flow through is coupled to the first conduit end, and the first conduit end has a clamping portion capable of clamping the flange of the filter vessel; a contact surface capable of strongly contacting to the inlet or the outlet of the filter vessel; and a guide member capable of, for a direction from the first conduit toward the inlet or the outlet, rotating about a second axis separated from a first axis by a predetermined distance, the first axis being from the first conduit toward the inlet, the guide member having a holding portion capable of holding the inlet or the outlet.

Filter vessel attachment/detachment apparatus

A first circuit outputs transmission signals that change between 'H' and 'L' in a period of an oscillation signal in addition to a transition time of an input signal when it changes to &#x201c;H&#x201d; or &#x201c;L&#x201d;. Control protection elements invalidate induced voltage signals obtained from transformers for first and second mask periods in response to transmission signals. Buffer circuits and Schmitt circuits generate a first signal and a second signal, each indicating &#x201c;H&#x201d; for a relatively long period, on the basis of &#x201c;H&#x201d; of the induced voltage signals. A control circuit invalidates the first signal and the second signal when both the first signal and the second signal indicate &#x201c;H&#x201d;.

Signal transmission circuit and power conversion device

This invention, is concerning a signal voltage device, in which transformersand a reception circuitare formed on the same chip, and accordingly, no ESD protective element connected to a transformer connection terminal of the reception circuitis required, and negative pulses generated in reception-side inductorscan be used in signal transmission. Signal transmission using both positive pulses and negative pulses is made possible as a result, and a stable signal transmission operation can be carried out even in a case where delay time varies in a signal detection circuit. Further, a reception circuit of low power consumption can be configured by using a single-ended Schmitt trigger circuitin the signal detection circuit.

Signal transmission device

The invention provides a method for the prophylaxis or treatment of hepatitis C in a mammal with a peptide-bound liposome wherein the peptide contains a partial amino acid sequence having a length of not less than 9 amino acids in the amino acid sequence of hepatitis C virus NS3 protein, has a length of 9 to 11 amino acids, and is capable of inducing cytotoxic T lymphocytes; the liposome contains a phospholipid containing an acyl group having 14 to 24 carbon atoms and one unsaturated bond or a hydrocarbon group having 14 to 24 carbon atoms and one unsaturated bond, and a liposome stabilizer; and the peptide is bound to the surface of the liposome. The invention also provides a cytotoxic T lymphocyte activator containing the peptide-bound liposome, as well as a hepatitis C virus vaccine.

Hepatitis C virus liposome vaccine

A signal transmission circuit includes, in each of a first circuit connected to a first coil of an insulating transformer and a second circuit connected to a second coil of the insulating transformer, a transmitting circuit, a receiving circuit, a coil-side switching circuit, an input/output-side switching circuit, an abnormality detection circuit, a delay circuit, and a direction control section. In the signal transmission circuit, the direction control section controls the switching circuit to switch a signal direction between input and output, and the switching circuit switches between transmission and reception. The delay circuit delays a received signal and returns the resultant signal to the transmitting side, and the abnormality detection circuit detects abnormality to perform self-diagnosis.

Signal transmission circuit and power conversion device equipped with same

The present invention aims to provide a novel CTL epitope peptide of the SARS coronavirus. The present invention provides a peptide having an amino acid sequence selected from the group consisting of SEQ ID NOs: 10, 11, 12, 13, 15, 17, 18, 23 and 24.

Cytotoxic T cell epitope peptide for SARS coronavirus, and use thereof

An injection compression molding method of a lens is provided, where a toggle link mechanism () is actuated to close a molding die () and a movable die plate () is moved to a position establishing a cavity thickness of greater than a thickness of an article to be molded while the die is closed. After injecting a molten resin into the cavity, the molten resin is sealed in the cavity and the toggle link mechanism () is actuated to advance the movable die plate () toward a fixed die plate (), the relative position of a rear die plate () and the movable die plate () is made constant at a position where extension of a tie bar () becomes a predetermined value, and the molten resin is cooled for a predetermined time after completion of pressurizing the resin.

Injection compression molding method of lens

The present invention provides an avian influenza vaccine containing a peptide-bound liposome wherein; the peptide contains:

Immunogenic compositions comprising liposomes and an influenza PB2 CTL epitope obtained from the highly pathogenic H5N1 strain

A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG.. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.

Semiconductor device with suppressed crystal defects in active areas

Injection compression molding method and injection compression machine of lens

An advertising information memory area for storing advertising information for displaying prescribed advertisement, and a label information memory area for storing label information for presenting a space for displaying advertisement, are provided. A personal computer refers the label information memory area and the advertising information memory area, synthesizes advertisement images and character strings based on the advertising information, and displays the same in the label image based on the label information. An advertising environment is provided which is highly effective in a personal computer environment.

Notification information display apparatus notification information display system and recording medium

There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not covered with the resist mask, and thereafter, forming a gate electrode and a source/drain diffused layer in a required well.

Method for manufacturing a semiconductor integrated circuit of triple well structure

To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses is performed by only one photoetching step, the process being capable of reducing the manufacturing cost, and speeding up the circuit operation by making the gate oxide film of the peripheral unit thinner than that of the I/O circuit unit. A resist mask having a given width ranging in a given range which will be formed on the silicon oxide film is formed in a gate forming area in a region where an embedded N-type layer will be formed in a P-type silicon substrate and it is desired to make the thickness of the gate oxide film thicker. The embedded N-type layer is also formed even immediately below the resist mask by conducting an ion implantation at a given energy via the resist mask. The oxide film is etched out by using the resist mask as a mask and the gate oxide film is then formed thereon.

Process for manufacturing semiconductor integrated circuit device

In a method of manufacturing a static memory device, a patterning process is performed to a lamination film composed of a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer with regions for load resistors. A lamination section of the first insulating layer and the first conductive layer are separated through the first and second patterning processes into first to fourth portions. The first and second portions respectively functioning as parts of the word line which are connected to each other and as the gates of the transfer MOS transistors, and the third and fourth portions respectively functioning as gates of the drive MOS transistors. The second conductive layer is separated through the second patterning process into fifth and sixth portions, and the fifth and sixth portions respectively functioning as parts of the power supply line which are connected to each other and as the load resistors connected to the parts of the power supply line. The fifth and sixth portions are laminated on a set of the first and third portions and a set of the second and fourth portions via the second insulating layer, respectively.

Method of making SRAM having part of load resistance layer functions as

A semiconductor static random access memory cell is implemented by four field effect transistors formed on a silicon layer over a buried silicon oxide layer and two resistors formed in an inter-level insulating structure; additional capacitors are formed under the buried silicon oxide layer, and are respectively connected to the gate electrodes of the field effect transistors serving as driving transistors of the memory cell so as to enhance the stability of the memory cell without increase the transistor size.

Semiconductor static random access memory cell with additional capacitor

Growing community of inventors

Tokyo, Japan

Tetsuya Uchida