Canon Kabushiki Kaisha

Tetsuya Tateno

Katsumi Otsuka

Susumu Igarashi

Yukio Chiba

Kenjiro Watanabe

Kimiyuki Hayasaki

Nobuyuki Hatasa

Tatsuhiko Yamazaki

Makoto Satoh

Makoto Sato

Koji Aoki

Keiji Ishizuka

Yuji Minami

Atsushi Furuya

An ink tank receives data signals from a printer and an LED provided on the ink tank is driven on the basis of the received data signals. The LED is driven in an inactive time period that is different from the time period in which the date signals are input to the ink tank.

Signaling module, liquid container, recording apparatus, and control method

In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information required for communication with the peripheral devices inside the relay apparatus; and command holding sections, which are provided adjacent to the communication information holding section, for holding commands used to communicate desired information inside the communication information holding section to the peripheral device. The CPU writes desired information in the communication information holding section and the command holding section inside the relay apparatus by burst-mode communication, and the relay apparatus performs communication with the peripheral devices in accordance with instructions from the command holding section after the writing of the desired information in the communication holding section and the command holding section is completed.

Relay apparatus for relaying communication from CPU to peripheral device

In image data coding and decoding processing, in order to improve efficiency by processing a plurality of factors in one cycle as long as possible, the factors are rearranged, in coding or decoding processing, in a predetermined scan sequence such that significant factors and 0s are paired. In addition, an appropriate scan sequence is selected in accordance with the distribution state of frequencies to further improve the efficiency.

Image coder/decoder, image coding/decoding method, and storage medium

A decoding apparatus has: M tables for storing, in correspondence with M types of variable-length code tables, minimum code words or maximum code words of classes of variable-length code words constructing a variable-length code table; a table selector which selects one table from the M tables; N comparators which compare input coded data with the minimum code words or maximum code words outputted from the table selected by the table selector; a switch circuit and a priority encoder which obtain a class number corresponding to an initial code word of the input coded data based on results of comparison by the N comparators; a code length converter which converts the class number into a code length; and an address generator which generates an address to access a memory holding decoded data from the class number and the code length outputted said code length converter. The data outputted from the memory based on the address becomes decoded data of the input coded data.

Decoding apparatus, method, and storage medium for inputting and decoding variable-length coded data

Whether a header information processor quickly enters a program inactive state at the timing when it issues an operation start command of an encoding process for a predetermined processing unit to a variable-length code encoder, or the header information processor enters the program inactive state upon completion of execution steps to be processed is adaptively selected in accordance with the number of execution steps. One memory is shared by the header information processor and variable-length code encoder, and address input permission means for controlling to grant permission of an address input to the memory to one of the header information processor and the variable-length code encoder is provided. The memory is used as a work area of the header information processor, and as a storage area of a variable-length code table which is looked up by the variable-length code encoder.

Image processing method, apparatus, and storage medium

This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means. For this purpose, in order to determine a code length and additional bit length, two different decode processes are executed, the overall process is separated into three stages, i.e., a stage for shifting out a code word of encoded data, a decode processing stage, and a symbol determination & additional bit processing stage, and these stages are executed in a pipeline manner.

Variable-length decoding apparatus and method

A decoding apparatus which efficiently stores information to determine an address value to read a decoded value from a decoded value memory. The apparatus performs decoding processing at a high speed, and further, reduces the memory capacity. The apparatus comprises a first storage for continuously storing decoded values for variable-length codes of the same code length; a second storage for storing an initial address in the first storage; a third storage for storing offset values between the initial address in the first storage and addresses for storing decoded values for variable-length codes of respective code lengths, respectively; a first specification unit for specifying a code length of an input variable-length code; a second specification unit for specifying the order of the input variable-length code among variable-length codes belonging to the specified code length; and an address generator for generating an address to read a decoded value from the first storage, based on the offset value corresponding to the code length specified by the first specification unit and the order specified by the second specification unit.

Decoding apparatus and method

A binarization processing apparatus for converting multi-value image data into binary image data is constructed by pixel groups in which pixels to be binarized are divided into a plurality of groups, a plurality of memories which correspond to the pixel groups and hold data in a binarization processing step, a control unit which performs the reading operation for one of the plurality of memories and simultaneously performs the writing operation for the other memory, and a unit for performing the converting process on the basis of an error diffusing method. The plurality of memories have a single common input/output port.

Binarization processing apparatus and method

A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.

Decoding apparatus and method therefor

An operational circuit device for calculating a plurality of bit data includes, an input unit for inputting a plurality of bit data, a constant current source provided for each of the plurality of bit data for generating a predetermined current in accordance with the bit data inputted from the input unit and a calculation unit for calculating a sum of the predetermined currents from the constant current sources.

Multiplication operational circuit device

An integrated circuit for level shift is a parallel-connected circuit comprised of a first circuit including a first MOS FET of one conductive type, a third MOS FET of another conductive type and a first MOS FET of the other conductive type which are series-connected in this order and a second circuit including a second MOS FET of the one conductive type, a fourth MOS FET of the other conductive type and a second MOS FET of the other conductive type which are series-connected in this order, wherein gates of the first and second MOS FETs of the one conductive type are connected respectively to the output side and input side of an inverter connected to a low voltage electric power source, gates of the third and fourth MOS FETs of the other conductive type both are connected to a reference voltage source, a gate of the first MOS FET of the other conductive type is connected to a common junction point of the fourth MOS FET and the second MOS FET of the other conductive type, a gate of the second MOS FET of the other conductive type is connected to a common junction point of the third MOS FET and the first MOS FET of the other conductive type, and the parallel-connected circuit is connected to a high voltage electric power source.

Integrated circuit for level shift

A semiconductor circuit is provided with a constant current circuit, a resistor network to which a current from the constant current circuit is supplied, and a device between the constant current circuit and the resistor network for switching the current supplied from the constant current circuit to the resistor network.

Growing community of inventors

Kanagawa, Japan

Tetsuya Tateno