Nec Corporation

Elpida Memory, Inc.

Nec Electronics Corporation

Tetsuya Taguwa

Yoshiaki Yamada

Toshiki Shinmura

Koji Urabe

Shunichiro Sato

A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on the first silicon layer; and a metal containing layer formed on the second silicon layer. The N-type gate electrode includes a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on the third silicon layer; and a metal containing layer formed on the fourth silicon layer. At least one of the second silicon layer and the fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of the first silicon layer and third silicon layer.

Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Method for manufacturing semiconductor device

A semiconductor device has a dual-gate electrode structure. The gate electrode has a layered structure including a doped polysilicon film, WSifilm, WN film and a W film. The WSifilm formed on the polysilicon film in the P-channel area is formed of a number of WSiparticles disposed apart from one another, preventing a bilateral diffusion of impurities doped in the polysilicon film.

Semiconductor device having a HMP metal gate

A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Semiconductor device having a low-resistance gate electrode

A processed object, i.e., a circuit-constituting member is positioned by a member-transferring unit at a given position in a member-waiting portion when plasma starts to be generated in a plasma-generative portion, and the circuit-constituting member is transferred from the member-waiting portion to the plasma-generative portion when the plasma started to be generated in the plasma-generative portion is brought into a stable condition thereof. Thus, the circuit-constituting member is not subjected to a circuit-processing by plasma before the stable condition is not reached but is surely subjected to the circuit-processing only by plasma in the stable condition.

Method of an apparatus for performing circuit-processing, method of and apparatus for controlling the motion of the circuit-processing performance apparatus, and information storage medium

A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer ) with good step coverage formed on a surface of a conductor film such as lower electrodes and of a capacitor on a semiconductor substrate is transformed into a reformed layer , which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.

Semiconductor device and method for manufacturing the same

There is disclosed a process for manufacturing a semiconductor device. When a metal film is formed by plasma CVD in a contact hole which penetrates an interlayer insulating film and reaches an electrode of the device, a gas comprising hydrogen and argon in a deposition chamber of a plasma CVD apparatus is introduced. Then a metal halide gas is introduced in the deposition chamber simultaneously with or before plasma generation.

Process for manufacturing a semiconductor device

A semiconductor integrated circuit device is implemented by circuit components and a multi-layered wiring structure, and titanium nitride is used for a part of the integrated circuit such as a conductive plug, an accumulating electrode and a conductive line, wherein the titanium nitride layer is laminated on a titanium silicide layer so as to absorb thermal stress due to the titanium nitride layer.

Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof

There is provided a method for manufacturing a semiconductor device having a barrier metal layer, including the steps of forming a titanium film as the barrier metal layer on a silicon oxide film, forming a titanium nitride film, and oxidizing a surface of this titanium nitride film, then the titanium nitride film is formed thereon. This titanium nitride film is formed as taking in oxygen from an underlying oxide film. Therefore, its crystal growth is inhibited and its barrier metal layer property is improved.

Semiconductor device having a barrier metal layer and method for manufacturing the same

A miniature contact is incorporated in a semiconductor device for transferring an electric signal between a conductive wiring and an impurity region, and a titanium silicide and a single crystal silicon region doped with an impurity forms an ohmic contact; in order to form the ohmic contact, a surface portion of the single crystal silicon region is made amorphous by using an ion-bombardment, thereafter, titanium is deposited on the amorphous silicon to have the thickness ranging between 3 nanometers and 10 nanometers, and the titanium layer is converted to a titanium silicide layer through an annealing at 400 degrees to 500 degrees in centigrade, thereby forming the low-resistive ohmic contact without changing the impurity profile of the single crystal silicon region.

Process of fabricating semiconductor device having low-resistive contact without high temperature heat treatment

A method of carrying out a plasma-enhanced chemical vapor deposition. A process gas is introduced into a reaction chamber containing a susceptor having a first region on which a semiconductor substrate is placed and a second region other than the first region, upon which a ceramics insulator is placed. A plasma is generated between the susceptor and an electrode, and a thin film is formed on the semiconductor substrate and on the ceramics insulator covering the second region of the susceptor. The resulting plasma-enhanced chemical vapor deposition results in enhanced uniformity of the thin metal film formed on the semiconductor substrate, and improved yield, and barrier characteristics.

Growing community of inventors

Tokyo, Japan

Tetsuya Taguwa