Hitachi, Ltd.

Renesas Technology Corp.

Tetsuya Shimomura

Yasuhiro Nakatsuka

Takashi Hotta

Koyo Katsura

Shigeru Matsuo

Kotaro Shimamura

Tatsuki Inuzuka

Kazushige Yamagishi

Nobuyasu Kanekawa

Fumio Murabayashi

Yuichiro Morita

Yutaka Okada

Manabu Jyou

Shigeya Tanaka

Hideo Sawamoto

Kazuyoshi Koga

The basic section of the multimedia data-processing system includes a CPU, an image display unit, a unified memory, a system bus, and devices, andconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unit. Main storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Memory access methods in a unified memory system

In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memoryis generated from the CPU, the memory controllerholds it once, requests the display controllerto stop the access to the memorywhich is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU buswhich is held by the memory. When the access from the CPU busends, the memory controllerrestarts the access stopped in the display controllerand passes the held data to the display controller

Data processor having unified memory architecture using register to optimize memory access

The basic section of the multimedia data-processing system includes a CPUan image display unita unified memorya system busand devicesandconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unitMain storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

Memory controller

In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU , the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory , holds it, and transfers the access request from the CPU bus which is held by the memory . When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller

Data processor having unified memory architecture providing priority memory access

In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.

Picture processing apparatus and picture processing method

An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them

In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.

An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

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Hitachi, Japan

Tetsuya Shimomura