Nec Corporation

Mitsubishi Denki Kabushiki Kaisha

Elpida Memory, Inc.

Tetsuya Ootsuki

Takaaki Iwata

Isao Naritake

A laser beam processing apparatus includes a laser oscillator for producing a laser beam for processing a processing object, a focus head for focusing the laser beam output from the laser oscillator onto the processing object, a photo detector for detecting light emanating from the processing object in response to irradiation with the laser beam and a reference light generated from a reference light generating unit via a nozzle attached to the focus head, a correlation adjusting unit for adjusting correlation between the light detected during the processing and processing state of the processing object from the reference light detected by the photo detector, and a control unit for controlling the laser oscillator by monitoring the processing situation of the processing object from the light detected during the processing and that is adjusted by the correlation adjusting unit.

Laser beam processing apparatus

In a semiconductor memory device, a plurality of memory cell arrays, and each of them includes a plurality of memory cells in a matrix. A mode control unit outputs a delay control signal, and an instruction execution unit accesses to the plurality of memory cells based on an address and an address buffer control signal supplied externally. A command control unit outputs the address buffer control signal to the instruction execution unit based on a command supplied externally and the delay control signal. The command control unit outputs the address buffer signal in synchronization with a clock signal when the delay control signal is in an inactive state and the command is a write command or a read command in an ordinary operation mode. When the delay control signal is in an active state and the command is the write command in a write instruction delay operation mode, also when the delay control signal is in the active state and the command is the read command in a read instruction delay operation mode.

Semiconductor memory device adaptive for use circumstance

There is provided a dynamic type semiconductor memory device including (a) a first hierarchized complementary bit line, (b) a second hierarchized complementary bit line, (c) a first sense-amplifier electrically connected to the first bit line, (d) at least one second sense-amplifier electrically connected to both the first bit line and the second bit line, (e) a capacitor located between the first and second bit lines for each of second sense-amplifiers, and (f) a transfer gate arranged in series with the capacity between the first and second bit lines. The above-mentioned dynamic type semiconductor memory device makes it possible to store two-bit data in a single memory cell by employing a memory cell comprised of one transistor and one capacitor, without the use of a conventional memory cell having two transistors and one capacitor. Hence, the dynamic type semiconductor memory device ensures a significant reduction in a chip area.

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Tokyo, Japan

Tetsuya Ootsuki