Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Ricoh Company, Ltd.

Gifu Sanyo Electronics Co., Ltd.

Tetsuya Okada

Mikitaka Tamai

Takahiro Yamashita

Hiroyasu Ishida

Eiji Satsuma

Hiroaki Saito

Yasuyuki Sayama

Tetsuya Yoshida

Makoto Oikawa

Kazunari Kushiyama

Seiji Miyoshi

Takaharu Ohira

Shoichi Toya

Hideyo Morita

Toshiharu Kokuga

Koichi Sogawa

Shigeyuki Murai

Akinori Suzuki

Kikuo Okada

Tadao Uehara

Katsuhiro Suzuki

Tohru Haruki

Masanori Miyata

Mitsuhiro Yoshimura

Kenji Nishihara

Toshitake Kurihara

Yuuichi Kohno

Taro Usami

Shisyo Chin

Hiroaki Teratani

Shiho Arimoto

Provided is a semiconductor device having an anode of a Si-FRD and a cathode of a Si-SBD which are serially connected. The Si-SBD has a junction capacitance whose amount of accumulable charge is equal to or more than an amount of charge occurring at the time of reverse recovery of the Si-FRD, and has a lower breakdown voltage than the Si-FRD does.

Semiconductor device comprising stack of pn junction diode and schottky barrier diode

In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n&#x2212; type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n&#x2212; type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n&#x2212; type semiconductor layer and the p type polysilicon layer in formation of the p type polysilicon layer can also reduce the amount of holes injected into the n&#x2212; type semiconductor layer. Thus, a time to extract the holes in reverse voltage application, that is, a reverse recovery time can be shortened without using a life time killer.

Diode with shortened reverse recovery time without reducing impurity concentration

An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Method of manufacturing semiconductor device

A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R, R, R, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T, T, T, . . . , Tx represent the polishing time T required for achieving a target film thickness when performing the flattening process by polishing each of the interlayer insulating films coating the projecting patterns; and a step of calculating, with the use of a formula T=(R&#x2212;b)/a, the polishing time T for the interlayer insulating films coating the projecting patterns having the area ratio R.

Chemical mechanical polishing method and chemical mechanical polishing device

Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

Semiconductor device

Two metal electrode layers are provided. A first electrode layer is patterned with a minute separation distance according to an element region as in the case of the conventional case. Meanwhile, it suffices that a second electrode layer be in contact with the first electrode layer. Thus, no problems arise even if the separation distance is elongated. Specifically, the second electrode layer can be set to have a desired thickness. Moreover, by disposing a nitride film on the first electrode layer below a wire bonding region, even when volume expansion is caused by an Au/Al eutectic layer, transmission of stress to the element region can be prevented.

Insulated gate semiconductor device and manufacturing method thereof

In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 &#x212b;. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.

A Schottky barrier diode in which a p-type semiconductor layer is provided in an n-type epitaxial layer can realize lowering the forward voltage VF without considering leak current IR. However, when compared with a normal Schottky barrier diode, the forward voltage VF is generally high. When a Schottky metal layer is suitably selected, although the forward voltage VF can be reduced, there is a limit in further reduction. On the other hand, when the resistivity of the n-type semiconductor layer is reduced, although the forward voltage VF can be realized, there is a problem that breakdown voltage is deteriorated. In a semiconductor device of the invention, a second n-type semiconductor layer having a low resistivity is laminated on a first n-type semiconductor layer capable of securing a specified breakdown voltage. P-type semiconductor regions are made to have depths equal to or slightly deeper than the second n-type semiconductor layer. By this, in a Schottky barrier diode in which leak current IR can be suppressed by pinch off of a depletion layer, the forward voltage VF can be reduced and the specified breakdown voltage can be secured.

Schottky barrier diode semiconductor device

In a semiconductor device, a variable-potential insulated electrode and a gate region are kept at the same potential through an aluminum layer. This device is mainly used as a voltage-driving type semiconductor device. By varying the voltage applied to the variable-potential insulated electrode through a gate electrode, a conductive path is formed in a channel region to switch on the device. The channel region turns into an N-type region when a positive potential is applied to the gate electrode, and turns into a pseudo P-type region when a ground potential or negative potential is applied to the gate electrode.

Remaining battery capacity is computed by computing battery discharge capacity from an integrated value of a product of discharge current and voltage to find remaining battery capacity via energy (integrated power). Battery discharge capacity is computed by adding the integrated value of power consumed by internal resistance to a discharge capacity value calculated from the integrated product of discharge current and voltage, and the remaining battery capacity is computed from this battery discharge capacity.

Method and apparatus for computing remaining battery capacity utilizing battery discharge capacity

This method to determine capacity of a battery computes capacity in current value and then converts it into capacity in power value, or computes capacity in power value and then converts it into current value. This method to determine capacity of a battery detects either discharge current or charge current or both, and computes capacity of battery in current value, which is then converted into capacity in power value by way of multiplication by the correcting constant which varies in accordance with capacity in current value. This method to determine capacity of a battery detects battery voltage or detects either discharge current or charge current or both of the battery, then computes battery capacity in power value, and converts capacity in power value so computed into capacity in current value by way of multiplication by the correcting constant which varies in accordance with capacity in power value.

Method to determine capacity of a battery

This method to determine remaining capacity of a rechargeable battery calculates remaining battery capacity by subtracting discharge capacity, computed by integrating battery discharge current, from charge capacity. Voltage of the discharging rechargeable battery is measured, and when battery voltage reaches a first voltage and a lower second voltage, the computed remaining battery capacity is corrected according to a previously established first remaining battery capacity and second remaining battery capacity corresponding to those voltages. The difference between calculated remaining battery capacity or discharge capacity at the first and second voltages is compared to the difference between the previously established first and second remaining battery capacity values, and the first voltage is modified to make those two differences equal.

Method to determine remaining capacity of a rechargeable battery

The battery charging apparatus is provided with a memory circuit for pre-storing correlation data between rechargeable battery charge capacity and time to completion of charging, a charge capacity measuring circuit to measure rechargeable battery charge capacity, and a calculating circuit to calculate, during charging, the time to completion of charging based on charge capacity determined by the charge capacity measuring circuit and correlation data stored in the memory circuit.

Battery charging apparatus which determines a time to completion of

The method of calculating rechargeable battery charge capacity of this invention has steps to temporarily interrupt charging and calculate battery internal impedance, to calculate a no-load battery voltage by subtracting the product of internal impedance and charging current from the battery voltage when charging current is supplied, to calculate charging power by multiplying no-load voltage and charging current, and to repeatedly perform the charging power calculation integrating that charging power result to compute battery charge capacity.

Method of calculating rechargeable battery charge capacity

A secondary battery is charged in alternating charging and pulse-charging periods in which the secondary battery is continuously charged during the charging periods and the secondary battery is charged in a series of charging pulses during the pulse-charging periods. The terminal voltage or the temperature of the secondary battery may be sampled during at least one interval between the pulses in a pulse-charging period to detect a full charge level or an excessive temperature, respectively. Such an arrangement can reduce charging time and facilitate accurate monitoring of the terminal voltage or the temperature.

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Sumoto, Japan

Tetsuya Okada