Renesas Electronics Corporation

Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Tetsuya Nitta

Shinya Soneda

Kazuma Onishi

Tadaharu Minato

Katsumi Morii

Yoshitaka Otsu

Shinichiro Yanagi

Kazuya Konishi

Mikio Tsujiuchi

Koichi Nishi

Takahiro Nakatani

Kosuke Yoshida

Tatsuya Shiromoto

Atsushi Sakai

Tomohide Terashima

Kenji Harada

Akihiko Furukawa

Hiroshi Kimura

Ryu Kamibaba

Yasuki Yoshihisa

Shigeo Tokumitsu

Munenori Ikeda

Tomohiro Tamaki

Takayuki Igarashi

Fumitoshi Yamamoto

Takahiro Mori

Shigeto Honda

Yasunori Yamashita

Kakeru Otsuka

Kikuo Kato

Atsushi Tachigami

Kazuya Horie

Akio Uenisi

Hajime Kataoka

Tatsuya Kawamata

Hironori Shimizu

A semiconductor device includes an insulated gate bipolar transistor region having a base layer of a second conductivity type provided in a surface layer of the semiconductor substrate on a first main surface side, an emitter layer of a first conductivity type having an impurity concentration higher than that of a drift layer selectively provided in the surface layer of the base layer on the first main surface side, a plurality of gate electrodes facing the emitter layer, the base layer, and the drift layer via gate insulating films, a counter-doped layer, having an impurity concentration of the second conductivity type higher than that of the base layer and an impurity concentration of the first conductivity type higher than that of the drift layer, and a collector layer of the second conductivity type provided in the surface layer of the semiconductor substrate on a second main surface side.

Semiconductor device

There is provided a technique capable of reducing turn-on power losses. A semiconductor device includes: a semiconductor substrate including a drift layer; and a base layer, a contact layer, and a source layer which are provided in the semiconductor substrate. A gate portion is provided in a first trench, with a first gate insulation film therebetween. The first trench is in contact with the contact layer, the source layer, the base layer, and the drift layer. The gate portion is provided with a recessed portion with a bottom farther away from the base layer than a side thereof. A first insulation portion is provided in the recessed portion of the gate portion in the first trench.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a first contact layer connected to a lower portion of a first trench contact portion and a second contact layer connected to a lower portion of a second trench contact portion. The distance between a first side portion of a first trench and the first trench contact portion is larger than that between a second side portion of the first trench and the second trench contact portion in a plan view, and the first contact layer is separated from the first side portion and the second contact layer is connected to the second side portion in a cross section. With this structure, it is possible to provide a technique for achieving an appropriate channel region.

An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n-type drift layer on the first main surface side of the n-type drift layer and having a higher n-type impurity concentration than the n-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n-type drift layer.

Semiconductor device and method for manufacturing the same

A semiconductor device includes an insulated gate bipolar transistor region and a diode region adjacent to each other, wherein the insulated gate bipolar transistor region includes base layers of a second conductive type provided on the first main surface side, emitter layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side, multiple gate electrodes provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer, the base layer, and the drift layer via a gate insulating film, carrier injection suppression layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side and sandwiched by the base layers in the first direction.

Semiconductor device with insulated gate bipolar transistor region and diode region provided on semiconductor substrate and adjacent to each other

Provided is a semiconductor device in which a first anode layer and a first contact layer are provided on a first main surface side in a diode region, and in which a second anode layer and a second contact layer are provided on the first main surface side in a boundary region. A concentration of impurities of a second conductive type of the second anode layer is lower than a concentration of impurities of the second conductive type of the first anode layer, or an occupied area ratio of the second contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the boundary region is smaller than an occupied area ratio of the first contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the diode region.

Semiconductor device including IGBT, boundary, and diode regions

A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer.

According to one aspect of the present disclosure, a semiconductor device includes a substrate; a drift layer of a first conductivity type provided on the substrate; a base layer of a second conductivity type provided above the drift layer on the substrate; a source layer of the first conductivity type provided on an upper surface side of the base layer; a first electrode electrically connected to the source layer; a second electrode provided on the rear surface of the substrate; a gate electrode; a trench gate extending from an upper surface of the substrate to the drift layer; and a first bottom layer of the second conductivity type provided below the trench gate in the drift layer, wherein a first distance between a portion of the first bottom layer where an impurity concentration peaks in a thickness direction and the trench gate is larger than 1 &#x3bc;m.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

Provided is a semiconductor device having improved breakdown resistance during recovery operation. A semiconductor device according to the present application is a semiconductor device in which an insulated gate bipolar transistor region and a diode region are provided adjacent to each other. The insulated gate bipolar transistor region includes an emitter layer having a short-side direction in a first direction in a plan view. The diode region includes carrier injection suppression layer having a short-side direction in a second direction in a plan view. In a plan view, a width of the carrier injection suppression layer in the second direction is smaller than a width of the emitter layer in the first direction.

An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

Semiconductor device and manufacturing method thereof

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.

A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

In a semiconductor device, a pback gate region (PBG) is arranged in a main surface (S) between first and second portions (P, P) of an nsource region (SR), and arranged on a side closer to an ndrain region (DR) with respect to the nsource region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Growing community of inventors

Kanagawa, Japan

Tetsuya Nitta