Fujitsu Corporation

Fujitsu Vlsi Limited

Tetsuya Nakajima

Hiroshi Shimizu

Akinori Tahara

Isao Amano

Takashi Iida

Satoru Sumi

Nobuyuki Tanaka

Taichi Saitoh

Minoru Takagi

Hideo Tokuda

Masaki Nagahara

Akio Kiso

Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Semiconductor integrated circuit with protection circuit against

A connecting structure for connecting conductors used for wiring in a semiconductor device comprises a first conductor provided on a part of the semiconductor device for passing the flow of electrons, an insulator provided on the first conductor and formed with a contact hole, and a second conductor provided on the insulator for passing the flow of electrons, in which the second conductor is provided so as to sandwich the insulator together with a part of the first conductor. The first and second conductors are contacted to each other across the insulator at the contact hole so that the electrons flow through the contact hole. The contact hole extends in a general direction of a flow of electrons passing therethrough and has a stepped shape in which a width measured perpendicularly to the general direction of the flow of electrons increases stepwise towards the general direction of the flow of electrons.

Connecting structure for connecting conductors in an electronic apparatus

A semiconductor memory device including at least word lines and bit lines with memory cells located at each cross point therebetween. Each of the word lines is divided to form segmented word lines and each of the word line segments is driven by an individual private word driver. The individual private word drivers are activated together in response to a word selection signal. Level shifting diodes are employed in the bit line drivers to offset a voltage level change caused by the segment word drivers.

Semiconductor memory with segmented word lines

Growing community of inventors

Kawasaki, Japan

Tetsuya Nakajima