Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Vlsi Engineering Corp.

Hitachi America, Ltd.

Nippon Telegraph and Telephone Corporation

Hitachi Maxell, Limited

Hitachi Microcomputer Engineering, Ltd.

Hitachi, Vlsi Eng. Corp.

Tetsuya Nakagawa

Atsushi Kiuchi

Toru Baji

Kenji Kaneko

Yoshimune Hagiwara

Yasuhiro Sagesaka

Hirotada Ueda

Koki Noguchi

Yuji Hatano

Jun Ishida

Tomoru Sato

Hajime Akimoto

Takao Watanabe

Yoshinobu Nakagome

Hitoshi Matsushima

Kouki Noguchi

Toshiaki Masuhara

Katsuhiko Ishida

Motonobu Tonomura

Akira Naito

Koichiro Ishibashi

Kazuo Yano

Yoshiyuki Kaneko

Yukio Nakano

Katsuhiro Shimohigashi

Toshihisa Tsukada

Osamu Minato

Muneaki Yamaguchi

Shiro Tanabe

Shigeki Masumura

Takashi Akazawa

Kazuo Ishikura

Hiroko Sukeda

Haruhiko Fujii

Masafumi Miyamoto

Hirotsugu Kojima

You Takamori

Kosaku Aida

Haruyasu Okubo

Noriyasu Suzuki

Atsuchi Kiuchi

Takanori Toyomasu

Masafumi Kunori

Eiji Kubo

Nobuya Kasai

Michi Kumagai

Mark Walton

In an asymmetric multi-CPU system on which a plurality of type of CPUs with different data processing performance and power consumption are mounted in groups for each type, a plurality of forms of combination of the types and numbers of CPUs are defined in such a way that the maximum numbers of the overall data processing and power consumption very by stages. Then, the system performs a control of allocation of the data processing to the CPU identified by the form selected from the definition information according to the data processing environment, in order to reduce unnecessary power consumption according to the data processing environment, such as data processing load, and to easily achieve the required data processing performance.

Multi-CPU system and multi-CPU system scaling method

A semiconductor device for realizing higher-precision noise elimination includes: a decoder which decodes an encoded input signal; a determining unit which determines whether or not a voice signal is included in the input signal; a suppressor which performs a suppressing process for suppressing a noise component included in the input signal on the basis of a result of determination by the determining unit; and a first storage for storing, as a determination criterion value used for the determination, a first criterion value which specifies the proportion of a voice signal with respect to voice distortion noise.

Semiconductor device and voice communication device

A user authentication method is applied to a user authentication apparatus for authentication using a unique ID that is information unique to a communication apparatus. The method includes acquiring a user ID as information identifying a user, and detecting a unique ID corresponding to the user ID from a user ID list. The method also includes making a call with a predetermined number of rings to a communication apparatus having the unique ID. Additionally, the method includes receiving a callback made by a communication apparatus after a predetermined number of rings of the call in response to the call. In addition, the method includes determining whether a unique ID of the communication apparatus having made the callback matches the unique ID of the communication apparatus to which the call has been made, and determining, if there is a match, that a user having the user ID is an authorized user.

Method, system, apparatus, and computer program product for user authentication

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core () integrated as a single bus master, an integrated external bus interface () and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Terminal apparatus

A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice when the video processing and the voice processing are separately performed by different processors.

Microprocessor and mobile communication terminal

A portable device having a communication function composed of a plurality of LSIs operated in synchronization with a clock, such as a baseband LSI and a logic LSI such as an application processor, can synchronize the baseband LSI with the logic LSI without lowering the performance of the logic LSI.

Radio communication semiconductor integrated circuit, data processing semiconductor integrated circuit and portable device

A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing. As a result, it is possible to provide a semiconductor device capable of generating a side tone without increasing the magnitude of a load borne by a CPU and without requiring an external circuit component.

Semiconductor device

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core ( ) integrated as a single bus master, an integrated external bus interface ( ) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master

Terminal

Microcomputer having data execution units mounted thereon

A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the operation program of the processor by replacing the software operation partially by the hardware. A practical application of this processor arrangement is found in mobile communication terminal devices including a digital cellular portable telephone in which a digital signal processor of a mobile communication terminal device operates in association with an accelerator for accelerating specific signal processings such as waveform equalization. The processor provides input data to the accelerator and the results of operation by the accelerator are output to a register or memory based on a cycle of operation to be read periodically by the processor. When the processor operates in association with the accelerator and is interrupted, the data output to the memory of the accelerator cannot be read by the processor and a clock control circuit is used for stopping the internal clock signal of the accelerator for stopping its operation. This avoids the potential for the operation of the accelerator to overwrite the output stored in the output register of the accelerator before it is read by the processor. The processor cannot read the output register of the accelerator while it processes an interrupt or when it loses ownership of the bus connecting the processor to the accelerator.

Data processing device having accelerator for digital signal processing

An electronic interpreter for interpreting sentences between a first person and a second person. The electronic interpreter includes a memory for storing sentence data in a data structure having a plurality of sets of sentences including translations of the sentences, wherein each sentence of each set of sentences is linked to another of the sets of sentences, and a data processing unit. The data processing unit retrieves a set of sentences from the memory in response to a keyword input from the first person using an input device, displays the set of sentences on a display, selects a sentence from the set of sentences in response to an input from the first person using the input device, displays a translation of the selected sentence on the display along with another set of sentences linked to the selected sentence, selects a sentence from the another set of sentences in response to an input from the second person using the input device, displays a translation of said selected sentence on the display along with another set of sentences linked to the selected sentence, and repeats all of the previous operations continually until a keyword has been input from the first person using the input device.

Electronic interpreter utilizing linked sets of sentences

A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits. Since the data lines of the two-dimensional memory array have the overlapped range, convolution processing operations or the like can be executed in parallel for the two-dimensional data stored in the two-dimensional memory array in a high parallelism and at a high speed.

Semiconductor IC with a plurality of processing circuits which receive

Growing community of inventors

Koganei, Japan

Tetsuya Nakagawa