Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Hitachi Microsoftware Systems, Inc.

Tetsuya Mochida

Koichi Okazawa

Kazushi Kobayashi

Hitoshi Kawaguchi

Koichi Kimura

Ichiharu Aburano

Takehisa Hayashi

Nobukazu Kondo

Seiji Kaneko

Hideaki Gemma

Masami Jikihara

Naoki Hamanaka

Naohiko Irie

Tetsuhiko Okada

Masabumi Shibata

Shigeo Tsujioka

Yasuhiro Ishii

Youichi Tanaka

Hiroaki Aotsu

Toshiaki Arai

Tomoki Sekiguchi

Hiromichi Enomoto

Tsuyoshi Watanabe

Kouichi Kimura

Tsutomu Noda

Yutaka Enko

Hitoshi Sadamitsu

Reki Yamamoto

Naofumi Shouji

Masataka Kobayashi

Kouichi Okazawa

Takanori Ishikawa

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Bus system for use with information processing apparatus

In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Bus control system

In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Multi-processor system and its network

Information processing system

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Growing community of inventors

Yokohama, Japan

Tetsuya Mochida