Oki Electric Industry Co., Ltd.

Tetsuya Mitoma

Norihiko Satani

Yuichi Matsushita

Shizuo Cho

Yasukazu Kai

Kenichiro Sugio

Yoshihiro Nakatake

A semiconductor integrated circuit device includes bit lines, a word line, a dummy word line, a memory cell, a dummy cell, a dummy word line drive circuit and a word line drive circuit. A dummy word line drive circuit is connected to the dummy word line. The dummy word line drive circuit supplies a precharge potential level that is higher than a first power supply potential level and a second power supply potential level that is lower than the first power supply potential level to the dummy word line. The word line drive circuit is connected to the word line. The word line drive circuit supplies the second power supply potential level and the precharge potential level to the word line.

Semiconductor memory device having a word line drive circuit and a dummy word line drive circuit

A voltage dropping power unit is provided which is capable of reducing power consumption in the voltage dropping power unit while a semiconductor memory device is placed in a quiescent state. The voltage dropping power unit is provided with a voltage control circuit to supply a dropped voltage controlled depending on a control voltage to the semiconductor memory device, a reference circuit to generate a reference voltage used to produce a control voltage and a differential circuit to make the dropped voltage equal to the reference voltage irrespective of a level of a voltage output from the voltage control circuit. The reference circuit has a voltage dividing resistor used to produce a reference voltage and a switching device used to form a short-circuit across the voltage dividing resistor.

Voltage-dropping power unit for semiconductor memory device

The present invention provides a semiconductor integrated circuit that solves the aforementioned problems. A semiconductor integrated circuit of the present invention has a plurality of memory cells, for respectively storing data, bit line pairs supplied with data read from the memory cells and sense amplifiers for amplifying data supplied to the bit line pairs. The integrated circuit also has first and second data bus driving transistors, and a pair of data buses. The first data bus driver transistors each have a control terminal, for receiving data supplied to one bit line of the bit line pairs, a second terminal connected to a common node, and a third terminal, while the second data bus driver transistors each have a control terminal, for receiving data supplied to the other bit line of the bit line pairs, one terminal connected to the common node, and a third terminal. The integrated circuit of the present further has a transfer circuit, connected between the pair of data buses and the third terminals of the first and second data bus driver transistors, for electrically connecting the third terminals to the pair of data buses in response to a row select signal, and an output control circuit, connected to a first power supply potential node supplied with a first power supply potential, a second power supply potential node supplied with a second power supply potential, and the common node, for selectively connecting the common node to either the first power supply potential node or the second power supply potential node, in response to a control signal.

Multi-bank semiconductor memory device having an output control circuit

A semiconductor memory device having two or more memory blocks is disclosed. The disclosed semiconductor memory device comprises first and second memory cores, first and second output circuits and internal output lines connected to the first and second output circuits, respectively. The first and second output circuits are respectively connected to said first and second memory cores for outputting the data in response to first and second control signals, respectively. The disclosed semiconductor memory device further comprises first and second control signal generating circuits. The first and second control signal generating circuits are connected to the first and second output circuits for generating the first and second control signals to the first and second output circuits. The first and second control signal generating circuits receive first and second read signals having the active state and the inactive state that is switched in response to a read control signal. The first and second control signal generating circuits switch the first and second control signals to the active state with a predetermined time delay when the first and second read signals are switched from the inactive state to the active state, while these immediately switch the first and second control signals to the inactive state when the first and second read signal are switched from the active state to the inactive state.

Semiconductor memory device having two or more memory blocks

A synchronous semiconductor memory device which prevents to misread due to the parasitic capacitance is disclosed. A synchronous semiconductor memory device of the present invention comprises memory cells for storing data therein, sense amplifiers coupled to the memory cells and pairs of data lines coupled to the sense amplifiers. The data lines extend to one direction so that the data lines are substantially parallel to each other. The pairs of data lines include first pairs of data lines and second pairs of data lines located between the first pairs of data lines. Each of the second pairs has a cross point at which each of the data lines of the pair crosses each other.

Synchronous semiconductor memory device

An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level. The second gate circuit has a first input node coupled to receive the second input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the first input signal and an output node coupled to the control terminal of the first transistor. The second gate circuit has the same circuit configuration of the first gate circuit.

Output buffer circuit

A semiconductor memory device according to the present invention comprises a first and second nodes, a first power supply for supplying a supply power potential to the first node, a memory cell for storing data therein; a bit line connected to the memory cell, a sense amplifier connected to the second node, for amplifying a potential of the bit line; a switching circuit connected between the first and second nodes, for coupling the first node with second node in response to a first control signal and substantial disconnecting the first node from the second node in response to a second control signal, a detecting circuit for detecting a potential of the second node and outputting a detection signal when the potential of second node is substantialy equal to the supply power potential, a control circuit applied an address signal having a first or second logic level thereto, for outputting the first control signal in response to the address signal being the first logic level and outputting the second control signal in response to the detection signal after the address signal being the second logic level.

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Miyazaki, Japan

Tetsuya Mitoma