Sony Corporation

Tetsuya Kondo

Tadakuni Narabu

Yasuhito Maki

Katsunori Noguchi

Maki Sato

Yoshihiro Kosugi

A CCD delay line comprises of first, second and third transfer regions which are formed in a semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region.

CCD delay line capable of automatic adjustment of an input bias voltage

A charge transfer device includes a first input stage converting a first input signal into first signal charge, a first shift register transferring the first signal charge with a first delay amount, a second input stage converting a second input signal into second signal charge and having a first switch for selectively inputting the second signal charge to a second shift register, a third input stage converting a third input signal into third signal charge and having a second switch for selectively inputting the third signal charge to a third shift register, and an adding section for selectively adding one of the second and third signal charge to the first signal charge. The second shift register transfers the second signal charge with a second delay amount and the third shift register transfers the third signal charge with a third delay amount.

CCD delay line with selective delay period circuit

A charge coupled device is provided with a first signal input path for supplying an information signal for transfer through a delay line, which contain an inverting amplifier, and a second signal input path which has no inverting amplifier. The first and second signal input paths are arranged in parallel to each other. The charge coupled device also has a switching means associated with the first and second signal input paths so as to selectively establishing connection between one of the first and second signal input paths and the delay line so that non-inverted and inverted information signals can be selectively supplied to the delay line.

Charge coupled device having switched inverting and non-inverting input

An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Charge coupled device with enhanced input structure

An output stage of a solid-state image pick-up device, such as a CCD solid-state image pick-up device is accurately operable even under a lower source source voltage is easy to design and does not require substantial precision in production. The improved output stage construction of a solid-state image pick-up device, according to the present invention, has a buffer circuit, connected to at least one of a input side or a output side of an output stage circuit component, such as an amplifier circuit, and a low-pass filter source source. The buffer circuit is so designed as to have a constant DC level and a gain about 1.

Output stage for solid-state image pick-up device

A charge transfer device, suitable for use, for example, in a solid state imager device, having a floating gate electrode in a charge detecting section, a protruding portion provided in at least one of the floating gate electrodes or a gate electrode arranged adjacent to the floating gate electrode, wherein the floating gate electrode and the gate electrode arranged adjacent to the floating gate electrode overlap each other at the protruding portion within an insulating layer, and whereby the parasitic capacitance associated with the floating gate electrode is decreased and the charge voltage converting gain is increased, rendering it possible to obtain an image signal with a good signal/noise ratio, when the charge transfer device is used for a solid state imager device.

Charge transfer device

A current generating circuit for dividing a current (Dynamic Element Matching) in which a portion of a plurality of transistors constituting change-over circuits arranged therein is removed by weighting the transistors for the operating periods thereof, to thereby largely reduce the number of elements, particularly in the case where a large number of bits are processed. Since the number of bits which each current generating circuit can process can be increased, the number of elements can be easily decreased, so that a source voltage can be reduced when the current generating circuits are connected in multiple stages (in a vertical piling). Further, transistors constituting switching circuits are connected in a Darlington configuration to expand the operating range (dynamic range) of the circuit.

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Kanagawa, Japan

Tetsuya Kondo