Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Tetsuya Kawakami

Yasushi Fukunaga

Tadaaki Bandoh

Jushi Ide

Hidekazu Matsumoto

Ryosei Hiraoka

Takeshi Kato

Kotaro Hirasawa

Hiroaki Nakanishi

Takeshi Katoh

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

Central processing unit for executing instructions of variable length

In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

Bus selection control in a data transmission apparatus for a

A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.

Data processing system

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

Shared virtual address translation unit for a multiprocessor system

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Hitachi, Japan

Tetsuya Kawakami