Renesas Electronics Corporation

Other

Tetsuya Katou

Mototsugu Okushima

Morihisa Hirata

Nobuhiko Ito

Susumu Kobayashi

Tomohiro Kitayama

Takeaki Etoh

Go Hata

A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate.

Semiconductor device having a lower-layer line

A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.

Semiconductor device and inspection method therefor

A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.

Semiconductor device including offset bonding pad and inspection method therefor

An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.

ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device

A semiconductor device of the present invention includes a plurality of switch cells having a switch transistor that controls conducting states of a global power supply line and a local power supply line according to a control signal, and a delay circuit that delays the control signal and transmits the control signal to the switch transistor connected to a subsequent stage, a chain unit that receives the control signal from outside, transmits the control signal by the delay circuit connected in series, and sequentially conducts the switch transistor, and a tree unit that is provided with the control signal via the switch cells disposed in a last stage of the chain unit, distributes the control signal to a plurality of groups by the delay circuit connected in parallel, and conducts the switch transistor in parallel by the distributed control signal.

Semiconductor device and control method of switch transistor thereof

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Semiconductor device with less power supply noise

A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring.

Semiconductor device including power supply pad and trunk wiring which are arranged at the same layer level

An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Growing community of inventors

Kanagawa, Japan

Tetsuya Katou