Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Showa Oil Company, Ltd.

Tokyo Shibaura Electric Co., Ltd.

Tetsuya Iida

Tatsuo Sakaue

Yasoji Suzuki

Junkei Goto

Chikara Sato

Fuminari Tanaka

Kazuhiro Tsuji

Yoshihiro Iwamoto

Masayuki Sahoda

Hiroshi Takakura

Naoki Sugawa

Takayoshi Ikarashi

Akira Yamaguchi

Takayuki Satoh

Takeshi Hitotsuyanagi

Hideo Saori

Hiroo Tominaga

Masao Inoguchi

Osamu Yamase

Ichizo Hara

Signal sources are arranged in a matrix form and provide preset analog values. Switching means are connected between signal sources and an analog output terminal having connection paths to the respective signal sources. Latch circuits are respectively provided for switch control circuits for controlling the switching means. Each of the latch circuits latches a control signal from a corresponding one of the switch control circuits and outputs the control signal in response to a preset synchronizing signal to a corresponding one of the switching means. The switching means are simultaneously controlled by output signals of decoders so that a desired analog output is permitted to be derived from the output terminal. The period of the clock signal can be shorten and a switching operation causing variation exceeding a desired variation occurring when the digital signal is changed can be prevented.

Digital to analog converter

A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

D/A converter having centered switching sequence and centered

This invention discloses an analog-to-digital converter. Current supply paths are branched at the current supply terminals from the other current paths so as to be connected exclusively to the analog voltage comparator. And a circuit block of the analog voltage comparator is positioned closer to the current supply terminals than the other circuit block of DA converter, sequential comparison register, etc.

Analog-to-digital converter with isolated power supply lines to the

To compensate for an offset of an A/D converter, a predetermined reference signal is supplied to the A/D converter. Based on the output signal of the A/D converter, the amount of the offset for this converter is acquired. A multiplexer outputs a compensation signal which serves to cancel out the acquired offset amount, the output of this multiplexer is subjected to analog addition to the analog input signal, and the offset of this A/D converter is compensated for at the input stage.

Successive approximation analog to digital converter

A signal interference prevention wiring is disposed between two wirings which are arranged in parallel for transmitting a signal, and the signal interference prevention wiring is held at a constant potential.

Semiconductor integrated circuit device

A successive approximation type A/D converter of the present invention has a capacitor having a predetermined capacitance value and arranged between an input terminal of a voltage comparator and a fixed potential terminal having a predetermined potential. According to the successive approximation type A/D converter of the present invention, the capacitor arranged between the input terminal of the voltage comparator and the fixed potential terminal having the predetermined potential prevents a potential at the input node of the voltage comparator from being greatly changed to exceed a power source voltage range due the influences of a local D/A converter when the sample mode is switched to the approximation mode. Therefore, the leakage of charges stored in the input side of the voltage comparator can be prevented. Accordingly, even if the amplitude of an analog input voltage is equal to the amplitude of the power source voltage, high-precision A/D conversion can still be performed.

Successive approximation type A/D converter

A level shift circuit is made up of a capacitor, a MOS inverter, and a bias circuit for applying a bias voltage to an input node of the MOS inverter. A first electrode of the capacitor is connected to an output stage of an ECL circuit, while a second electrode to the input node of the MOS inverter. The output node of the MOS inverter is coupled with an input stage of a CMOS circuit. An output signal of the ECL circuit is capacitively coupled with the input node of the MOS inverter so that it is superposed onto a bias voltage being supplied from the bias circuit. A level of this signal is shifted to a CMOS logic level by the MOS inverter, and then applied to the input stage of the CMOS circuit.

Level shift circuit for converting a signal in an ecl level into a

An A/D converter of this invention includes a first A/D converter for A/D-converting the input signal and determining upper bits of the n-bit binary code, first and second sample-hold circuits, which are alternately switched each time the first A/D converter samples the analog input signal, for sampling and holding the analog input signal, in synchronism with a sampling timing of the first A/D converter, and a second A/D converter. The second A/D converter is constituted by a reference voltage generator for generating reference voltages, based on contents of the binary code obtained by the first A/D converter, a voltage comparator for comparing the reference voltage with a voltage value of the analog input signal held in one of the first and second sample-hold circuits, which sample and hold the analog input signal corresponding to the binary code, and an encoder for encoding a comparison result output from the voltage comparator and determining lower bits of the n bits.

Pipelined serial-parallel A/D converter

A digital-to-analog converter includes a group of resistors serially connected between a power source potential supply terminal and a reference potential supply terminal. First group switches are connected between a first circuit point and given serial connection nodes of the resistor group, and between the first circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding upper bits of a digital signal. Further, second group switches are connected between a second circuit point and other serial connection nodes of the resistor group, and between the second circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding lower bits of the digital signal. First and second capacitors are connected between an output terminal and the first circuit points, and between the output terminal and the second circuit point, respectively.

Compact R segment D/A converter

A voltage comparator circuit that is useful in A/D converters and D/A converters. The circuit comprises a comparison capacitor, a holding capacitor and input switching transistors. The holding capacitor holds the comparison voltage applied to it from the input switching transistors through the comparison capacitor. Therefore, the circuit can perform accurate voltage comparison even if the input voltages are sampled at a high sampling frequency.

High frequency voltage comparator circuit

A digital-to-analog converter of current segment type, having a plurality of first variable current sources and a second variable current source of the same structure as the first variable current sources. The converter further comprises a comparator. The comparator compares a voltage corresponding to the output current of the second variable current source with a reference voltage. The difference between these compared voltages is used to determine the output currents of the first variable current sources.

Digital-to-analog converter

In the comparator circuit, the amplifier circuit is comprised of an inverting amplifier section having a high gain and a noninverting amplifier section having a low output impedance. Therefore, the comparator circuit has a high input sensitivity. The comparator circuit can also operate at a high speed.

Voltage comparator circuit

A sample-and-hold circuit has an impedance converter, a first switch, an amplifier, an input circuit for receiving an input signal and supplying an output signal corresponding to the input signal to the amplifier, through the impedance converter and the first switching means, output-holding capacitor coupled between the input and output terminals of the amplifier, and a feedback circuit coupled between the output terminal of the amplifier and the input terminal of the impedance converter. The input circuit and the feedback circuit are a first switched capacitor and a second switched capacitor, respectively.

Sample-and-hold circuit

In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.

Highspeed parallel adder with clocked switching circuits

A synchronous binary circuit comprising a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, first logic means for feeding, to J and K input terminals on each of flip-flops among the lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among the lower bit stage flip-flops, and third logic means for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, the third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of the flip-flops lower than the second stage and a fourth logical product, and the fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in the higher bit stage flip-flops.

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Yokohama, Japan

Tetsuya Iida