Mitsubishi Denki Kabushiki Kaisha

Tetsuya Iga

Koichi Hasegawa

Naoyuki Kato

A timing generating circuit (9) receives a reference signal (f.sub.REF) and an operation control signal (S.sub.0) as inputs and outputs a generation control signal (S.sub.1). The generation control signal (S.sub.1) is inputted to the prescaler (31), the programmable divider (41) and a phase comparator (51). The generation control signal (S.sub.1) goes 'H' when the operation control signal (S.sub.0) goes 'H' and then the reference signal (f.sub.REF) is counted predetermined times, and a raw signal (f.sub.RAW) is divided to start generating a signal to be measured (f.sub.0) after the generation control signal (S.sub.1) goes 'H', so that a phase difference .delta. between the reference signal (f.sub.REF) and the signal to be measured (f.sub.0) at the start is constant irrespective of the timing of the operation control signal (S.sub.0) attaining 'H'. Accordingly, it is not necessary to set the timing of the operation control signal (S.sub.0) attaining 'H' considerably earlier prior to a period required in the time-division telegraphy, and the power consumption of a prescaler (31) and a programmable divider (41) are suppressed.

Phase-locked loop circuit

There is disclosed a PLL circuit wherein a delay circuit (3') of a phase comparator (30') receives a supply current (IC) from a first variable current source (.PHI.IC) and changes a delay time (.DELTA.T) in negative correlation with the amount of the supply current (IC), and the first variable current source (.PHI.IC) changes the amount of the supply current (IC) to the delay circuit (3') in accordance with the indication of a control signal (C1) serving as a supply current control signal for a second variable current source (.PHI.IA) and a third variable current source (.PHI.IB) of a charge pump circuit (31). Changes in delay time of the delay device of the phase comparing device are adapted such that the delay time is constantly suitable as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.

PLL circuit

A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.

Semiconductor integrated delay circuit

A flip-flop circuit of ECL structure includes an ECL circuit portion and a level shift circuit portion including a circuit having a pair of resistors. The ECL circuit portion applies a differential signal to one end of each of the resistors, and Q and/Q output signals are derived from the other ends of each of the resistors. The amount of level shift down of the signals when shifted by the resistors is enabled to be set to any relatively small amount, whereby the ECL circuit is permitted to operate at a low voltage.

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Itami, Japan

Tetsuya Iga