Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Tetsuya Heima

Akira Ohta

Norio Higashisaka

Akira Inoue

A first transistor has a first terminal and a second terminal. A second transistor has a third terminal, a fourth terminal and a fifth terminal electrically connected to the second terminal of the first transistor during amplification performed by the first transistor. A first bias circuit is electrically connected to the first terminal of the first transistor and supplies a first bias to the first terminal so that a magnitude of the first bias is increased with a rise in circuit temperature. A second bias circuit is electrically connected to the third terminal of the second transistor and supplies a second bias to the third terminal so that the magnitude of the second bias is constantly maintained with respect to changes in the circuit temperature.

Multistage amplifier

An inductor has a laminated structure in which an insulating layer and a wiring layer are laminated alternately on a semiconductor substrate. The laminated structure includes at least two wiring layers and an insulating layer interposed between them. A first wiring layer has a first winding part and a second winding part in the same plane, adjacent each other, and wound. A second wiring layer has a wiring part having a single path from one terminal to the other. The first and second winding parts are electrically connected to the wiring part. When a voltage is applied between one terminal of the first winding part and one terminal of the second winding part, currents flow in the first and second winding parts in opposite directions.

Inductor having small energy loss

A high frequency power amplifier with reduced power loss and improved power amplification efficiency has an output matching circuit providing an open circuit to a second harmonic and a short circuit to a third harmonic of a high frequency signal. This is accomplished by, for example, adjusting lengths of a drain bias line and a plurality of signal lines so that the phase of S parameter S11 (input reflection coefficient) to the second harmonic is from &minus;80&deg; to 140&deg;, and the phase of S parameter S11 to the third harmonic is from 160&deg; to 220&deg;. The line length of each line in an input matching circuit is also adjusted so that the phase of S parameter S22 (output reflection coefficient) at the fundamental frequency is between &plus;5&deg; to &minus;75&deg;.

High frequency power amplifier

A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

Variable delay circuit

A semiconductor device includes an input terminal and an output terminal; a delay circuit including N (N=integer) unit delay circuits connected in series between the input terminal and the output terminal, earn unit delay circuit including first and second two-input NOR or NAND circuits connected in series, the second two-input NOR or NAND circuit being nearer to the output terminal than the first two-input NOR or NAND circuit, a first input of each first two-input NOR or NAND circuit being connected to the input terminal, and an output of each first two-input NOR or NAND circuit being connected to a first input of the second two-input NOR or NAND circuit of each unit delay circuit; and a control circuit outputting individual control signals, each control signal being applied to a respective second input of the second two-input NOR or NAND circuit included in each unit delay circuit, wherein delay time in signal transmission from the input terminal to the output terminal varies in response to the control signals. The number of elements per unit resolution is reduced, and variations in the delay time are reduced by the reduced element number so the linearity of the delay circuit is improved. Further, the layout is simplified as compared with the conventional delay circuit.

Semiconductor device

A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.

Growing community of inventors

Tokyo, Japan

Tetsuya Heima