Sony Corporation

Sony Semiconductor Solutions Corporation

Japan Science and Technology Agency

Tetsuya Fujiwara

Hiroaki Fujita

Hiroaki Nakano

Uichiro Omae

Yosuke Ueno

Shinichirou Etou

Shingo Harada

Yusuke Tanaka

Kazuyuki Aihara

Naoya Arisaka

Norihito Suzuki

Yoshihiko Horio

Makoto Masuda

Hiroya Yamamoto

Yoshiaki Mori

Tsutomu Kurihara

There is provided an oscillation device includes multiple delay elements that each sequentially delay an input signal, and return at least some of the delayed signals to a preceding stage to generate an oscillation signal. The oscillation device further includes a first control terminal that inputs, to the multiple delay elements, a direct current control signal for collectively controlling direct current voltage levels of the input signal to be input in plural number to the multiple delay elements.

Oscillation device and PLL circuit

In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.

Phase locked loop, electronic device, and method for controlling phase locked loop

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

Time-to-digital converter and phase locked loop

The present technology relates to a phase-locked loop that allows a reduction in power consumption. A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.

Phase-locked loop

The present technology relates to a first edge detector that detects whether there is an edge of a second clock signal in one cycle of a first clock signal. A second edge detector detects whether there is an edge of the first clock signal in one cycle of the second clock signal. The logic circuit performs a logical operation on a detection result from the first edge detector and a detection result from the second edge detector. The present technology can be applied to a circuit or the like that detects a locked state of a PLL circuit, for example.

Detection device and detection method

A communication device of the disclosure includes a phase synchronizer, a modulator, and a controller. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner by selectively performing one of a closed loop operation and an open loop operation. The modulator is able to modulate the first signal on a basis of the second signal. The controller controls operations of the phase synchronizer and the modulator.

Communication device, communication method, and communication system

A communication device of the disclosure includes a phase synchronizer, a first modulator, and a detector. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner. The first modulator is able to modulate the first signal on a basis of the second signal. The detector detects that synchronization between the first signal and the second signal is lost.

Communication device, communication method, and communication system with desynchronization detection

A circuit includes first and second capacitances arranged on a first path that connects first and second terminals; a first switch arranged between the first capacitance and the second capacitance; a second switch arranged on a second path that connects a reference voltage section and a first node formed between the first capacitance and the first switch; a third switch arranged on a third path that connects the section and a second node formed between the second capacitance and the first switch; a first resistance arranged on a fourth path that connects the first node and a third node formed between the first terminal and the first capacitance; a second resistance arranged on a fifth path that connects the second node and a fourth node formed between the second terminal and the second capacitance; a fourth switch on the fourth path; and a fifth switch on the fifth path.

Circuit, voltage control oscillator, and oscillation frequency control system

Disclosed herein is a phase-locked circuit including: a phase-locked section including a voltage controlled oscillator having a capacitance bank and changing oscillation frequency according to voltage information, the phase-locked section phase-locking an oscillating signal of the voltage controlled oscillator to a reference signal; and a calibration section having a voltage correcting function for supplying an appropriate calibration voltage to the voltage controlled oscillator in performing frequency calibration for the voltage controlled oscillator; the calibration section including a counter circuit, a first storage circuit and a second storage circuit, a comparator circuit, a control circuit, a voltage generating circuit, and a processing circuit.

Phase-locked circuit and radio communicating device

An oscillation circuit includes: n ring oscillators each formed from m delay elements connected annularly, m being an integer equal to or greater than 2, n being an integer equal to or greater than 2; and a phase coupled ring.

Oscillation circuit and recording apparatus

A phase-locked loop circuit includes a phase detection unit, a loop filter unit including a series circuit of a resistor and a capacitor, first and second pulse-current output units which supply differential and single-end pulse currents corresponding to phase information to the resistor and capacitor, an oscillating unit which varies an oscillation frequency in accordance with a voltage generated at the resistor and capacitor, and a calibration unit which obtains information of an oscillation gain in actual operation and corrects an operation of the oscillating unit on the basis of a difference between the oscillation gain in actual operation and a target oscillation gain. The oscillation gain in actual operation represents a characteristic of oscillation frequency versus input signal of the oscillating unit and is obtained using predetermined oscillation control signals on the basis of a difference between actual oscillation frequencies under the oscillation control signals.

Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic apparatus

A phase-locked loop circuit includes a phase detection unit which detects phase information of an input signal, a loop filter unit including a series circuit of a resistor and a capacitor, first and second pulse-current output units which supply pulse currents corresponding to the phase information output to one and the other of the resistor and the capacitor, and an oscillating unit capable of varying an oscillation frequency in accordance with a component obtained by combining a voltage generated at both ends of the one of the resistor and the capacitor on the basis of the pulse current supplied from the output terminal of the first pulse-current output unit and a voltage generated at both ends of the other one of the resistor and the capacitor on the basis of the pulse current supplied from the output terminal of the second pulse-current output unit.

An N-shaped nonlinear resistor circuit using floating gate MOSFETs; to realize various N-shaped characteristics that can be approximated by piecewise linear functions of third to seventh orders and further to realize N-shaped V-I characteristics that can variously change those characteristics by use of external voltages. A &#x39b;-type nonlinear resistor circuit (1) and a V-type nonlinear resistor circuit (2) using multi-input floating gate MOSFETs are connected in parallel, and the currents of the &#x39b;-type and V-type nonlinear resistor circuits are added together, thereby providing various N-shaped voltage-current characteristics.

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Kanagawa, Japan

Tetsuya Fujiwara