Kabushiki Kaisha Toshiba

Fuji Xerox Co., Ltd.

Casio Keisanki Kabushiki Kaisha

Toshiba Memory Corporation

Amway Corporation

Tetsuya Fujita

Nobuo Hyakutake

Yoshihiro Enomoto

Hiroyuki Hara

Masaaki Tokunaga

Fumio Furusawa

Nobuyoshi Komatsu

Keiji Yamamoto

Tadahiro Kuroda

Mototsugu Hamada

Fumitoshi Hatori

Satoshi Fukada

Shinichiro Shiratake

Toshio Nakai

Satoru Torimaru

Hitoshi Funato

Yasuo Nakamura

Yukihito Oowaki

Hiroaki Awano

Takayasu Sakurai

Jun Abe

Masataka Matsui

Shigeru Inaba

Hirotsugu Kajihara

Yousuke Hagiwara

Junichi Hama

Hidekiyo Tachibana

Masashi Kajimoto

Keiji Maruyama

Yutaka Toyoda

Hiromi Noro

Mikio Yamamoto

Kazuhiko Miyazato

Kazuhiro Yoshihara

Masaaki Fukuhara

Gensoh Matsubara

Toshio Endo

Kouichi Harada

Motosugu Hamada

According to one embodiment, a semiconductor memory device includes, a memory cell array, a first clock signal line, a second clock signal line to which first and second input/output buffer circuits are coupled in the order from one end toward the other end, a first buffer coupled to the one end of the second clock signal line, and a second buffer coupled to the other end of the second clock signal line. When a write operation is performed, a clock signal is input to the first and second input/output buffer circuits through the first buffer, and when a read operation is performed, a clock signal is input to the first and second input/output buffer circuits through the second buffer.

Semiconductor memory device

A transfer device includes a transport belt that contacts with a photoreceptor, and transports a recording medium; a transfer roll that transfers the toner image formed on a surface of the photoreceptor to the recording medium while pressing the recording medium to the photoreceptor through the transport belt; an adjusting unit that adjusts a pressing force of the transfer roll against the recording medium; and a controller that controls the adjusting unit so that a first pressing force is stronger than a second pressing force. The first pressing force is the pressing force after the recording medium starts to pass through a transfer position of the transfer roll and is moved by a predetermined distance. The second pressing force is the pressing force when the recording medium starts to pass through the transfer position.

Transfer device, non-transitory computer readable medium, image forming apparatus, and transfer method

A semiconductor integrated circuit includes a first power supply line to which an input power supply voltage is to be applied, a second power supply line configured to supply a bias voltage to a load circuit, a MOS transistor having a source-drain current path connected between the first and second power supply lines, an NMOS transistor having a source-drain current path connected between the first and second power supply lines, and a control circuit configured to generate a first control signal that is supplied to a gate electrode of the PMOS transistor at a first point in time, and a second control signal that is boosted to have a voltage level higher than the input power supply voltage and then supplied to a gate electrode of the NMOS transistor at a second point in time point that is after the first point in time.

Power gating circuit

An image forming apparatus includes an image carrier member, an intermediate transfer member, a transfer unit, a cleaning unit, and a driving controller. The image carrier member carries a toner image. The toner image carried on the image carrier member is first-transferred to the intermediate transfer member. The transfer unit second-transfers the toner image first-transferred to the intermediate transfer member onto a recording medium. The cleaning unit removes residual toner on the intermediate transfer member after the second transfer. The driving controller changes a driving time of the intermediate transfer member after completion of image formation in accordance with information about a life of the intermediate transfer member.

Image forming apparatus having belt drive control

According to one embodiment, a power source controller has a first power source line supplied with a reference power source voltage, a second power source line connected to an internal circuit, a control circuit configured to control a connection between the first power source line and the second power source line, a control signal line connected to the control circuit, and configured to provide a control signal for controlling the connection, a transistor comprising a first terminal, a second terminal and a control terminal in the control circuit, the control terminal of the transistor being connected to the control signal line, a semiconductor substrate on which the transistor is formed, and first through third wires.

Power source controller and semiconductor integrated circuit

A post-processing device include a conveyed medium stacking portion, a medium bundle stapling member, a medium bundle stacking portion and a medium bundle stacking control unit. A plurality of recording mediums, on which images are recorded, are conveyed and stacked into the conveyed medium stacking portion. The medium bundle stapling member staples a medium bundle, which is a bundle of the plurality of recording mediums stacked on the conveyed medium stacking portion, with staples. The stapled medium bundle is conveyed and stacked into the medium bundle stacking portion. The medium bundle stacking control unit stacks a second medium bundle on a first medium bundle under the condition that a second stacking stapling position deviates from a first stacking stapling position in a width direction by a distance not less than a staple width.

Post-processing device

A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.

Semiconductor integrated circuit device

A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.

Power supply voltage controlling circuit and semiconductor integrated circuit

This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Semiconductor integrated circuit and source voltage/substrate bias control circuit

According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

Semiconductor device and system

A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

Semiconductor integrated circuit having controller controlling the change rate of power voltage

This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

Voltage comparator circuit capable of precisely comparing voltages to ground and power supply potentials, without level converter or plurality of power supplies. First and second MOS transistors, with gates commonly connected and drains are connected to a first power supply potential with the same gate width and length. Third MOS transistor with opposite conductive type than first and second, with drain connected to second power supply potential connected to source of first. A fourth MOS transistor with opposite conductive type to the first and second, with a drain connected to the second power supply potential, with same gate width and length as the third. The drain and gate of the first are connected, and a comparative reference potential applies to the gate of the third. Input signal is given to gate of the fourth, and output signal is derived from the drain of the second.

Voltage comparator circuit and substrate bias adjusting circuit using same

Semiconductor device

A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around &minus;2 V.

Semiconductor integrated circuit

Growing community of inventors

Kawasaki, Japan

Tetsuya Fujita