Kabushiki Kaisha Toshiba

Tetsuya Asami

Yutaka Tanaka

Youichi Satou

Takehiro Hashimoto

Noriaki Okumiya

Masakazu Kakumu

In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively. The testing semiconductor device has main features (design rules, MOSFET structure, wiring structure, etc.) common to the types included in its corresponding type group, and a failed portion thereof, if any, can be easily detected by an analysis using a tester.

SRAM-based semiconductor integrated circuit testing element

Semiconductor integrated circuit device, method of estimating failure ratio of such devices on the market, and method of manufacturing the devices

A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, forming a high impurity concentration layer of a second conductivity type in the surface area of a portion of the semiconductor substrate defined by the element isolation region, and forming a first insulation film on the entire surface of the resultant semiconductor structure. Thereafter, a contact hole is formed in the first insulation film which is formed on the high impurity concentration layer, a semiconductor layer containing an impurity of the same conductivity type as the high impurity concentration layer is formed on the first insulation film, and a second insulation film is formed on the semiconductor layer. After this, a planarization film is formed on the entire surface of the second insulation film and is then selectively removed by anisotropic etching, to leave part of the planarization film filling the contact hole. Then, the portion of the planarization film exposed by the anisotropic etching is removed, a metal layer is formed on the entire surface of the resultant semiconductor structure, and the metal layer and semiconductor layer are patterned to form a laminated structure of a wiring layer.

Method for forming contact portion in semiconductor integrated circuit

Growing community of inventors

Kawasaki, Japan

Tetsuya Asami