Mitsubishi Denki Kabushiki Kaisha

Tetsuya Aono

Hiroshi Miyamoto

Tadato Yamagata

Shigeru Mori

Michihiro Yamada

Yutaka Ikeda

Akio Nakayama

Koichi Nagase

Yoshinori Mizugai

An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.

Semiconductor memory device and method for controlling its output

There is disclosed a DRAM having a 16 bit configuration which can be used for either a 2CAS/1WE type or a 1CAS/2WE type. The type of DRAM to be used is determined by whether there is a connection through a gold wire between a predetermined bonding pad and a lead for ground potential. Depending on the state of the connection of the bounding pad, conversion buffer converts externally applied control clock signals to internal control clock signals for either the 2CAS/1WE or the 1CAS/2WE. A clock generator not shown is operated in response to the converted internal control clock signals. The type of DRAM to be used is determined by whether there is a connection through a gold wire which is provided at the final step in a manufacturing process, so that the manufacturing processes are unified and therefore the type of DRAM to be used can be altered quickly depending on a drastically changing demand. In addition, efficiency in manufacturing a DRAM is enhanced.

Dynamic random access memory allowing determination of a read/write

A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.

Substrate bias circuit having substrate bias voltage clamp and operating

The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1. Therefore, malfunctions of the address buffer 1 can be prevented.

Growing community of inventors

Hyogo, Japan

Tetsuya Aono