Nec Corporation

Nec Electronics Corporation

Tetsuya Akimoto

Morihisa Hirata

Junko Matsumoto

Miyuki Yamamoto

A timing analysis apparatus in an integrated logical circuit according to the present invention includes a jitter information generation unit for generating period jitter information of an operational clock in response to a power supply/ground noise, a jitter information storage unit for storing the generated period jitter information, and a timing analysis unit for performing a timing analysis of the integrated logical circuit based on the stored period jitter information.

Timing analysis apparatus and method of timing analysis

In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.

Method of delay calculation in integrated circuit, and timing analysis system using the same

To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Method and computer software product for calculating and presenting a numerical value representative of a property of a circuit

A design automation method is provided which reduces complication of design work resulting from individual verification of a plurality of objects to be verified, for example, electromigration and hot carrier effect. Limiting values are prepared individually for the objects to be verified while a combined limiting value is obtained by combining these limiting values. By the use of the combined limiting value, verification of reliability is performed for all the objects. Specifically, when applied to the electromigration and the hot carrier effect as the objects to be verified, verification can simultaneously be performed upon frequency limiting values for the electromigration and the hot carrier effect.

Design automation method and device

In a method for verifying a timing at an object logic cell between a first signal and a second signal in a logic circuit with a plurality of logic cells including the object logic cell, there are determined first delay data of the first signal from a first external input terminal to the object logic cell, first waveform slew data of the first signal to the object logic cell and first signal data indicating a frequency, duty ratio and jitter of the first signal and a second waveform slew data of the second signal to the object logic cell. A first portion of a first waveform of the first signal and a second portion of a second waveform of the second signal is calculated in time then it is determined whether the first portion of the first waveform overlaps the second portion of the second waveform.

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Tokyo, Japan

Tetsuya Akimoto