Sharp Kabushiki Kaisha Corporation

Tetsuya Akamatsu

Masanori Inamori

Hiroki Doi

Haruya Mori

Hideki Shioe

A semiconductor integrated circuit, including: a logic section; an initiating current generating section for generating initiating current for initiating or re-initiating a circuit when the circuit is to be initiated or the circuit operates abnormally; an initiating current detecting section for detecting the initiating current of the initiating current generating section and outputting a detection signal indicating whether or not the initiating current generating section operates normally; and a signal selection section for selecting one of the detection signal and an output from the logic section based on an internal signal of the logic section which is controllable from outside of the logic section, and outputting the selected one to a terminal.

Semiconductor integrated circuit, test method and electronic information device

A semiconductor integrated circuit is so structured that a first insulating layer is formed on a surface of a semiconductor chip and a second insulating layer covers an entire region of the surface of the semiconductor chip. Via apertures made to the second insulating layer, an electrical connection configuration is formed from above the second insulating layer by using gold wires. Then, an electronic component is mounted on the second insulating layer. By arranging as such, the electronic component is mounted on the semiconductor chip in advance. Therefore, it is possible to further reduce mounting space on a printed-wiring board and also possible to make is easy to attain one-packaged IC.

Manufacturing method for semiconductor integrated circuit, semiconductor integrated circuit, and semiconductor integrated circuit apparatus

A power-on reset circuit comprises a power supply voltage detection circuit that detects a rise of a power supply voltage and that changes a logic level of a first internal node; a capacitor charge/discharge circuit that charges and discharges a capacitor according to the first internal node level and that in an event that the power supply voltage is reduced, discharges the capacitor to follow the event; and a reset pulse generation circuit that before the power supply voltage rises higher than the predetermined voltage, outputs a first output voltage to an output node and that after the power supply voltage has risen higher than the predetermined voltage, outputs a second output voltage to the output node upon detecting that a charge level of the capacitor has become higher than a charge level detection voltage.

Growing community of inventors

Tenri, Japan

Tetsuya Akamatsu