Fuji Electric Co., Ltd.

Denso Corporation

Tetsutaro Imagawa

Seiji Momota

Takeshi Fujii

Hitoshi Abe

Koh Yoshikawa

Soichi Yoshida

Makoto Asai

Takashi Shiigi

Masaki Koyama

Tomoyuki Obata

Yasushi Ookura

Shun Sugiura

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

Semiconductor device

Provided is a semiconductor device having a transistor portion and a diode portion, including: a drift region of a first conductivity type provided in a semiconductor substrate; an accumulation region of a first conductivity type provided on a front surface side of the semiconductor substrate with respect to the drift region in the transistor portion and the diode portion; and a first lifetime control region provided on the front surface side of the semiconductor substrate in the transistor portion and the diode portion.

Semiconductor device and manufacturing method of the same

A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

Between a source electrode () of a main device () and a current sensing electrode () of a current detection device (), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator () is larger than a product of the resistor and maximal current flowing through the current detection device () with reverse bias. A diffusion length of a p-body region () of the main device () is shorter than that of a p-body () of the current detection device (). A curvature radius at an end portion of the p-body region () of the main device () is smaller than that of the p-body () of the current detection device (). As a result, at the inverse bias, electric field at the end portion of the p-body region () of the main device () becomes stronger than that of the p-body region () of the current detection device (). Consequently, avalanche breakdown tends to occur earlier in the main devicethan the current detection device ().

Provided is a testing apparatus for testing a semiconductor device including a first main terminal to which a first power source voltage is applied and a second main terminal to which a second power source voltage is applied, comprising: a condition setting unit for setting a changing speed of a terminal voltage of the first main terminal at turn-off of the device; an operation controlling unit for turning off the device under a condition set by the condition setting unit; and a determining unit for screening the device based on an operation result of the device, wherein: a time waveform of the terminal voltage at turn-off of the device includes a maximum changing point where a changing speed becomes maximum; and the condition setting unit sets the changing speed at a first set voltage higher than a voltage at the maximum changing point, to a predetermined value.

Testing apparatus, testing method, and manufacturing method

Semiconductor device using regions between pads

There is provided a method of manufacturing a semiconductor device including: forming a cell having a plurality of trench portions, a contact region, being formed by implanting a dopant of a second conductivity type by a first depth and a first implantation amount, and an emitter region, the cell having a length, which is smaller than or equal to a width between the trench portions, the emitter region, having a length, which is greater than a length of the contact region; forming a contact hole, having an opening width which is smaller than the length of the contact region; and forming a plug region by implanting the dopant of the second conductivity type by a second depth, being shallower than the first depth, and a second implantation amount, being greater than or equal to the first implantation amount, in the depth direction of the semiconductor substrate.

Method of manufacturing semiconductor device and semiconductor device

A semiconductor layer of a first conductivity type has a plurality of impurity concentration peaks that are differently positioned in a first direction extending from a first surface to a second surface, and an integrated concentration obtained by integrating an impurity concentration value in the first direction from (i) the first surface that is a junction interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type to (ii) a boundary between a first impurity concentration peak of the plurality of impurity concentration peaks that is the closest to the first surface and a second impurity concentration peak of the plurality of impurity concentration peaks that is the second closest to the first surface is equal to or lower than a critical integrated concentration.

Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of gate trench sections formed in the semiconductor substrate; and a plurality of emitter trench sections formed in the semiconductor substrate, one or more emitter trench sections provided in each region between adjacent gate trench sections of the plurality of gate trench sections, wherein the semiconductor device includes at least one of: pairs of gate trench sections in which at least two gate trench sections of the plurality of gate trench sections are connected; and a pair of emitter trench sections in which at least two emitter trench sections of the plurality of emitter trench sections are connected.

A semiconductor device includes: a semiconductor substrate having an element; a front surface electrode connected to the element; a rear surface electrode connected to the element; a protective film disposed on the front surface of the semiconductor substrate in a separation region; and a temperature sensor disposed on a front surface side of the semiconductor substrate. The front surface electrode is divided into multiple pieces along at least two directions with the protective film. The separation region includes an opposing region located between opposing sides of divided pieces of the front surface electrode adjacent to each other, and an intersection region, at which the opposing region intersects. The temperature sensor is disposed in only the opposing region.

Growing community of inventors

Matsumoto, Japan

Tetsutaro Imagawa