Fujitsu Corporation

Tetsutaro Hashimoto

Tetsuyoshi Shiota

A TDC measures a time difference between delay time that is in accordance with voltage variations. A DCOgenerates an oscillation signal having a cycle that is in accordance with an input signal. A frequency dividergenerates a divided signal by dividing the oscillation signal. An adderinputs, to the DCOa signal obtained by adding a second signal that changes an oscillation cycle of the DCOin accordance with the time difference measured by the TDC to a first signal that is in accordance with a phase difference between the divided signal and a reference signal. A control circuitobtains a measurement time resolution of the TDC and matches a cycle modulation time resolution of the DCOwith the measurement time resolution of the TDC.

Information processing device, information processing method, and computer-readable recording medium

An electronic circuit is described including an oscillator generating an oscillating signal having a cycle responsive to an input signal, a voltage detector producing a detection signal responsive to a power supply voltage, a frequency divider generating a frequency-divided signal obtained by dividing a frequency of the oscillating signal by a frequency-division ratio responsive to the detection signal, and an adder obtaining a sum of a first signal and a second signal and to supply a signal responsive to the sum to the oscillator as the input signal. The first signal is responsive to a difference in phase between the frequency-divided signal and a reference signal, and the second signal is responsive to the detection signal. A related method is also described.

Electronic circuit for controlling an oscillator, and related method

A digital filter includes: a minimum-value holder that holds a minimum value of a measurement value inputted in the minimum-value holder and that outputs the minimum value as a held value; a limit-value circuit that receives the held value and that outputs the held value as a limit value in a case where the held value remains minimum during predetermined cycles; and an output controller that receives a maximum value, the measurement value, and the limit value, the maximum value defining an upper limit, outputs the measurement value as an output value if the measurement value is smaller than the limit value, and outputs the maximum value as the output value if the measurement value is equal to or larger than the limit value.

Digital filter and timing signal generation circuit

A voltage regulator circuit includes: a first pulse generator configured to output a pulse whose level remains unchanged when an input signal of a first circuit is in a first period, and whose level changes from a second level to a first level when an edge of the input signal of the first circuit is detected after the first period; a second pulse generator configured to output a pulse from a time that the pulse output by the first pulse generator becomes the first level until a second period elapses; a first field-effect transistor having a source connected to a power supply potential node, and a drain connected to a power supply potential terminal of the first circuit; and a first switch configured to cause a potential at a gate of the first field-effect transistor to be a first potential.

Voltage regulator circuit including pulse generators

A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in transistor performance among the plurality of delay elements.

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Kawasaki, Japan

Tetsutaro Hashimoto