Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Other

Ryoden Semiconductor System Engineering Corporation

Tetsushi Tanizaki

Kazutami Arimoto

Fukashi Morishita

Mitsuya Kinoshita

Katsumi Dosaka

Takahiro Tsuruda

Takeshi Fujino

Mako Kobayashi

Teruhiko Amano

Mikio Asakura

Masaru Haraguchi

Masaki Tsukude

Takayuki Miyamoto

Tetsuo Kato

Masami Nakajima

Kiyohiro Furutani

Takashi Kono

Takeshi Hamamoto

Yasuhiro Konishi

Hideyuki Noda

Shigehiro Kuge

Shigeru Kikuda

Kazushi Sugiura

Yasumitsu Murai

Yukikazu Matsuo

Katsuya Furue

Takayuki Gyoten

In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.

Parallel operational processing device

A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.

Semiconductor device including test-facilitating circuit using built-in self test circuit

A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.

Test circuit capable of testing embedded memory with reliability

A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

Semiconductor memory device with built-in self test circuit operating at high rate

A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device

In the semiconductor memory device, a control circuit generates various commands for a memory cell array according to an internal command control signal and an internal address signal output from an input switching circuit for switching an input source of the command control signals and the address signal between an external terminal and a BIST circuit. In the BIST mode, the input switching circuit cuts the signal input from the external terminal and generates the internal command control signal and the internal address signal according to an output signal from the BIST circuit. Transition to the BIST mode and return to the normal operation mode are indicated by a combination of signals supplied to the external terminal. Therefore, an interface between a built in BIST circuit and other internal circuits can be secured without an addition of a special interface specification.

Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification

A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.

Circuit for reducing test time and semiconductor memory device including the circuit

A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.

Semiconductor memory device having a circuit for fast operation

In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.

Semiconductor test circuit for testing a semiconductor memory device having a write mask function

A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.

Semiconductor memory device

A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes. Therefore, because the for-synchronization-circuit enabling signal is not received from the outsides but is produced, a circuit area of a semiconductor integrated circuit can be efficiently used.

Semiconductor integrated circuit having built-in self-test circuit

A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.

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Hyogo, Japan

Tetsushi Tanizaki