Hiroshima University

Semiconductor Technology Academic Research Center

Tetsushi Koide

Hans Juergen Mattausch

Hans Jurgen Mattausch

Tetsuo Hironaka

Yuki Tanaka

Hans Jürgen Mattausch

Koh Johguchi

Takashi Morimoto

Youmei Harada

Tai Hirakawa

Tsubasa Mishima

Md Anwarul Abedin

Masahiro Mizokami

Akihiro Kaya

Hiroshi Uchida

Zhaomin Zhu

Yuji Yano

Kosuke Yamaoka

Masakatsu Ishizaki

Takeshi Kumaki

Yoshinori Shirakawa

HoangAnh Tuan

Wataru Imafuku

Tania Ansari

Seiryu Sasaki

Masahiro Yasuda

Masaharu Yamamoto

Hoang Anh Tuan

Kouki Sugi

Rie Miyaki

Tsubasa Hirakawa

Toru Tamaki

Satoshi Shigemi

Shigeto Yoshida

An endoscopic image diagnosis support system () includes: a memory () that stores learning images pre-classified into pathological types; and a processor () that, given an endoscopic image, performs feature value matching between an image of an identification target region in the endoscopic image and the learning images, to identify the pathological types in the identification target region. The processor () performs feature value matching between images of the identification target region and subdivided regions of the identification target region and the learning images to compute identification probabilities of the pathological types in the identification target region and the subdivided regions, and computes average values of the identification probabilities of the pathological types in the identification target region and the subdivided regions, the average values corresponding to identification probabilities of the pathological types in hierarchical overlap regions of the identification target region and the subdivided regions.

Endoscopic image diagnosis support system for computing average values of identification probabilities of pathological types

In a symbol recognition device, each histogram computation module receives an image of each partial region of a recognition target region in a binarized image and computes a frequency distribution of pixels of a given color in each line or column in the partial region; each run length determination module receives an image of each partial region of the recognition target region and determines whether or not a line or column of pixels of the given color having a certain length is present in the partial region; a control module feeds pixel information of the partial regions, read by scanning the binarized image stored in the image memory, into the histogram computation modules and the run length determination modules; a determination module determines a symbol included in the binarized image based on computation results of the histogram computation modules and determination results of the run length determination modules.

Symbol recognition device and traffic sign recognition device

An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DTto DT. The R distance/time conversion circuits DTto DTeach include a NAND circuitand N bit stagestok. The N bit stagestok delay a signal from the NAND circuitby longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DTto DT, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.

Associative memory

An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.

An offset removal circuit () includes a removal circuit () and a removal circuit (). The removal circuit () digitally removes offset voltage from an input voltage Vin. The removal circuit () removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (). Then, the removal circuit () outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier ().

Offset removal circuit, associative memory including the same, and offset voltage removal method

Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Associative memory and searching system using the same

The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.

Reference data optimization learning method and pattern recognition system

A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.

Compression processing apparatus and compression processing method

A pixel-value detecting circuit () detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (). When both of two adjacent pixels have achromatic color, the connection weight determining circuit () determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit () determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit () determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues. An image segmenting circuit () segments the input image into images of subjects by using the connection weight determined by the connection weight determining circuit ().

Image segmentation apparatus and image segmentation method

An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VIto VI), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and a control circuit generating a control voltage (CONTROL) that follows a minimum voltage or a maximum voltage of the plurality of input voltages (VIto VI) from outputs of the plurality of differential amplifiers and supplying the generated control voltage (CONTROL) as a common value to the other inputs of the plurality of differential amplifiers.

Amplifier circuit and associative memory

A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Multi-port integrated cache

In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.

Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit for processing an image

In an associative memory, when a reference data having the minimum distance with respect to an input data is detected as winner, it is determined whether or not a distance between the input data and winner is less than a threshold value. If the distance is less than the threshold value, it is determined that the reference data detected as winner matches with the input data, and then, a rank of the reference data is improved. If the distance is more than the threshold value, it is determined that the reference data is data different from the input data, and then, the input data is written as new reference data to the associative memory and replaces the reference data with the lowest rank. The upper positions of rank form as a long-term memory, and the lower positions thereof form as a short-term memory.

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Higashihiroshima, Japan

Tetsushi Koide