Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Tetsurou Toubou

Toshiyuki Moriwaki

Keiichi Kusumoto

Nana Okamoto

Tsuguyasu Hatsuda

Junichi Yano

Kazuyuki Nakanishi

Hidetoshi Nishimura

Mitsuaki Hayashi

Takashi Ando

Kenji Shimazaki

Akio Hirata

Hiroki Taniguchi

Miwa Ichiryu

Hiroyuki Shimbo

Hisako Yoneda

A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width Wlarger than a cell width of cell A-1, but gate length Lof a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width Wequal to a cell width of cell B-1, but has a MOS transistor having large gate length L. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression

A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment

In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the cells includes an impurity doped region for supplying a substrate or well potential NWVDD which is different from a positive power supply potential VDD to a p-type transistor arranging region. The reinforcing power supply cell includes a power supply impurity doped region to which an impurity doped region of an adjacent cell is electrically connected and a power supply wire provided in a wiring layer formed above the power supply impurity doped region and electrically connected to the power supply impurity doped region.

Layout structure of semiconductor device

There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

Semiconductor integrated circuit device having a dummy metal wiring line

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to 'a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.

Signal transmission circuit

A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Growing community of inventors

Hyogo, Japan

Tetsurou Toubou