Fujitsu Corporation

Tetsuro Okamoto

Shigeaki Okutani

Keiichiro Uchida

Kazushi Sakamoto

Noriaki Kume

Norio Inui

Hiroshi Tamura

An information processing system including an arithmetic unit in which one unit of data is processed according to a corresponding one instruction, and another arithmetic unit in which a great amount of data are processed according to a corresponding instruction. Also included is an instruction controller which distributes instructions selectively to respective arithmetic units (12) and a main storage (12) which achieves two-way data communication with the arithmetic units. In the system synchronization is performed with respect to instructions, among the aforesaid instructions, which, above all, must be executed in respective fixed execution sequences, by utilizing a newly employed synchronization instruction. Further, the aforesaid instructions are classified, in dependence upon the execution sequence, into first instructions which are to be executed under a serial processing mode and second instructions which can be executed under a parallel processing mode, by inserting both a serialized-starting instruction (POST) and a serialized-releasing instruction into the aforesaid instructions.

Vector data processing system with instruction synchronization

The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.

Data processing system for parallel processing of different instructions

The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Bank interleaved vector processor having a fixed relationship between

A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

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Machida, Japan

Tetsuro Okamoto