Hitachi, Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Hitachi Displays, Ltd.

Hitachi Device Engineering Co., Ltd.

Other

Tetsuro Izawa

Tetsuya Kawamura

Nobuyuki Ishige

Yoshihiro Imajo

Shiro Ueda

Kimitoshi Ohgiichi

Fumiaki Komori

Hiroshi Okawara

Hisashi Ishino

Iwao Takemoto

Toshio Miyazawa

Shigeki Nishizawa

Atsushi Hasegawa

Katsumi Matsumoto

Tatsuhisa Fujii

Kenji Kitajima

A liquid crystal display includes pixels each having an switching element, drain drivers and gate drivers for operating the switching elements and the pixels, and drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer. Wiring lines are formed on the one of a pair of substrates for transferring display data signals and a clock signal to the gate drivers.

Driving method for display device

In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the plurality of drain drivers. This liquid crystal display device has an advantage, for instance, or of suppressing electromagnetic interference (EMI) to another equipment surrounding the liquid crystal display device, of preventing the display data signals or the clock signal from being distorted in the wiring lines.

Display device

Liquid crystal display device

Herein disclosed is an amplification circuit for realizing a substantially high sensitivity with a simple structure. The amplification circuit comprises: a first capacitor C1 for receiving a signal charge; a source-follower circuit for receiving a voltage of the first capacitor C1; an inversion amplification circuit including a source-earth type amplification MOSFET Q5 having its gate fed with the output signal of the source-follower circuit through a second capacitor C2; a feedback third capacitor C3 connected between the gate and drain of the amplification MOSFET Q5; and a switch element Q6 for feeding the gate of the amplification MOSFET Q5 with a predetermined bias voltage while the signal charge of the first capacitor C1 is being reset. The amplification MOSFET Q5 has its drain equipped as load means with a depletion type MOSFET Q4 having its gate and source connected, and the depletion type MOSFET Q4 has its source given the same potential as the substrate potential thereof.

Output circuit for a CCD with cascode depletion MOSFET loads and a

Disclosed is an MOS solid-state imaging device including a source-follower FRT amplifier in each picture-cell and a capacitor in each row for differentially directing output signals to cancel offset parameters such as those due to deviations of manufacturing caused during the process.

Solid-state imaging device with an amplifying FET in each pixel and an

A noise reduction circuit receives a periodic signal from an imaging device, and includes first and second circuits in which noise components opposite in phase are offset by delaying the input signal to produce a delayed signal and adding the delayed signal and the input signal. The output of the first circuit is supplied to a low pass filter, while the output of the second circuit is integrated through a first high-pass filter for a time wherein an output signal representing the sum of the input signal and the delayed signal is generated and is then outputted through a second high pass filter. Output signals of the low-pass filter and the second high-pass filter are then added and the result is outputted as a signal free noise.

Noise reduction circuit for an imaging and recording apparatus with an

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Mobara, Japan

Tetsuro Izawa